A question about variable thing

[ZHIQUAN]

Hello, everyone


I have a question to ask.Please leave your comments. Many thanks

Here it is:

strd3:=strd2;
strd2:=strd1;
strd1:=strd;


if the value of strd from '0' changes to '1';

Does only strd1=1, and others still keep the inital value. I suppose
all the variable values are '0'；

I guess if it is correct, when strd='1'
strd3=0;
strd2=0;
strd1=1;
and next cycle period,

strd3=0;
strd2=1;
strd1=1;

Do you think I am correct on this thing? Many thanks.

 

[Andy]

Yes you are correct.

Synthesis infers a register for a REFERENCE to a variable, if that
reference is executed before any assignment in the same clock cycle
(i.e. if it would have to remember the value from the last clock
cycle.). It is important to remember that the variable itself can
represent combinatorial and/or registered values, based on relative
position/timing of assignment and reference.

Andy

ZHIQUAN wrote:

Hello, everyone


I have a question to ask.Please leave your comments. Many thanks

Here it is:

strd3:=strd2;
strd2:=strd1;
strd1:=strd;


if the value of strd from '0' changes to '1';

Does only strd1=1, and others still keep the inital value. I suppose
all the variable values are '0'；

I guess if it is correct, when strd='1'
strd3=0;
strd2=0;
strd1=1;
and next cycle period,

strd3=0;
strd2=1;
strd1=1;

Do you think I am correct on this thing? Many thanks.