A question about syntax of VHDL

[Jim Huang]

Can I write the if condition like this? Assume

signal A std_logic_vector(29 downto 0);

if A = (others => '0´) then
.................
end if;

if this syntax is invalid, how should I write it? any simple way.
I do not want to put 30 zeros here.

Can I write the condition as
A = "00" & 0x0000000

Thanks
Jim

 

[dutchgoldtony]

An assignment takes the form if A<= (others => '0');

 

[Jim Huang]

Hi

Thanks, but I think you misunderstood me. I asked if I can compare the
signal A with (other => '0') in the IF clause.

 

This form will work:

if Sig = (Sig'range => '0') then

This is from comp.lang.vhdl "Frequently Asked Questions" Part 1. This
very useful document can be found at http://vhdl.org/comp.lang.vhdl/.

Best regards,

Charles

 

[Mohammed A khader]

HI Jim,

if A = (others => '0´) then

will give you error as

others must be use with constrained array. (others => '0') is not
enough to know the length of the array.

Can I write the condition as
A = "00" & 0x0000000

Yes you can write the numbers in hex or oct

if ( A = X"0000") then -- will work fine but make sure that type A
is a vector of bit or std_logic.

-- Mohammed A Khader.

 

[Mohammed A khader]

HI Jim,

if A = (others => '0´) then

will give you error as

others must be use with constrained array. (others => '0') is not
enough to know the length of the array.

Can I write the condition as
A = "00" & 0x0000000

Yes you can write the numbers in hex or oct

if ( A = X"0000") then -- will work fine but make sure that type A
is a vector of bit or std_logic.

-- Mohammed A Khader.