A question about "+" operator

Hi all,
I'm new to Verilog and my question is as follows:
What is the difference between the following two lines of code -

1. if (wr_ptr == rd_ptr + 1) ....
2. if (wr_ptr == rd_ptr + 1'b1) ....

When I uses the first one my simulator (Modelsim) doesn't behave as
expected but when I use the second one it gives me the wanted result.

Can anyone help me here ?

Thanks in advance, Moti.

 

[Neo]

I dont think it should behave differently but just in case try putting
braces around the rd_ptr +1 and check..

 

info_ wrote:

if (wr_ptr == rd_ptr + 32'b1) !!!
If I'm correct, the RHS is extended to at least 32 bits (probably
unsigned, I don't
have the code declaring the vectors).

Yes, that would be correct. Because of the 32 bit constant, rd_ptr and
wr_ptr will get extended to 32 bits before the calculation begins.

2. if (wr_ptr == rd_ptr + 1'b1) ....
No size extension occurs.

Well, the 1'b1 will get extended to the (presumably wider) width of
wr_ptr and/or rd_ptr, but of course you didn't mean the constant.

So with 8 bits vectors, ff + 1 = 100 and ff + 1'b1 = 00

Yes, which presumably explains the difference.

 

Thanks a lot for this answer I understand it now but it gets me to
think about the following:

When implementing a counter I write ->

always @(posedge clk)
if (clk)
cnt <= cnt + 1;

Here it works fine even when I write < + 1 > instead of < + 1'b1 >

Can you please explain me the difference?

Thanks again, Moti.

 

moti@terasync.net wrote:

Thanks a lot for this answer I understand it now but it gets me to
think about the following:

When implementing a counter I write -

always @(posedge clk)
if (clk)
cnt <= cnt + 1;

Here it works fine even when I write < + 1 > instead of < + 1'b1

Can you please explain me the difference?

In both cases the addition evaluates to the same value. In
the case of the comparison, the result of the addition is an
intermediate value which takes its width from the size of
the operands. In the case of the assignment, the extra bit
is thrown away, so in the case of an 8-bit counter:

8'hff + 32'h00000001

still evaluates to 9'h100, but only the 8 low bits are used
in the assignment (cnt is defined as 8 bits and not augmented
as would be an unnamed intermediate value in an expression)
but all 9 bits will be used for the comparison.

Thanks again, Moti.

 

Thanks a lot - as I mentioned earlier I'm new to verilog - and I guess
that I have to do some more reading
But the subject is a lot clearer now.

Moti.

 

It actually evaluates to 32'h100, but as you say the important thing is
that it gets truncated back to 8 bits when it gets assigned back to cnt.