a question about fsm confusing me for a long time

[anny]

I am designing a state machine that will be fit into a FPGA.
The state machine have 9 states.Every state except idle state needs to
wait certain number of clockes (
for example, 80 clockes here,or maybe longer ,even 1000 clockes ). I
use counter in every state to hold current state.My question is I need
to load the counter in every state and counting,how can I seperate
the counter from the state ?When counting to 1000 clocks,the system
frequence is low,how to resolve it?
my code:
always @ (posedge clock)
case(cs)
idle: cs<=s0;
s0: begin
if(count==79) begin
count<=0;
cs<=s1;
end
else
count<=count+1'b1;
end
s1:.......

 

[Mike Treseler]

anny wrote:

I am designing a state machine that will be fit into a FPGA.
The state machine have 9 states.Every state except idle state needs to
wait certain number of clockes (
for example, 80 clockes here,or maybe longer ,even 1000 clockes ). I
use counter in every state to hold current state.

No. I expect the state and delay variables will have
to be declared separately.

My question is I need
to load the counter in every state and counting,how can I seperate
the counter from the state ?

Declare multiple variables.
If the counters run concurrently, you will need separate
variables for them as well.

When counting to 1000 clocks,the system

frequence is low,how to resolve it?

No. The system clock is constant.
Your code traverses the block once every clock cycle.
The counters and state variables are updated once per clock.
Outputs can change (or not) on each rising clock edge.

-- Mike Treseler

 

[Andy]

On Sep 12, 2:04 pm, anny <zqr_...@163.com> wrote:

I am designing a state machine that will be fit into a FPGA.
The state machine have 9 states.Every state except idle state needs to
wait certain number of clockes (
for example, 80 clockes here,or maybe longer ,even 1000 clockes ). I
use counter in every state to hold current state.My question is I need
to load the counter in every state and counting,how can I seperate
the counter from the state ?When counting to 1000 clocks,the system
frequence is low,how to resolve it?
my code:
always @ (posedge clock)
case(cs)
idle: cs<=s0;
s0: begin
if(count==79) begin
count<=0;
cs<=s1;
end
else
count<=count+1'b1;
end
s1:.......

Generally, when I do state machines with timed waits in states, I have
a down counter timer that decrements by default, unless loaded via the
state machine. I set the timer value in the state before I transition
to the wait state, then in the wait state, I don't transition to the
next state until the timer gets to 0.


Sorry, this is vhdl...

-- decrement timer by default
count <= (count - 1) mod max_count;

case state is
when init=>
state <= s0;
count <= 79; -- set wait time for s0
when s0 =>
if count = 0 then
state <= s1;
count <= 1000; -- set wait time for s1
end if;
when s1 =>
...
end case;


Andy