A question about an example SystemVerilog code

[Robert Willy]

Hi,

I don't know why it shows

# 1990ns is current time

for the lower part system Verilog code.


Could you explain it to me?


Thanks,



/////////////////
# 1990ns is current time
# ** Note: $finish : C:/Users/rj/Documents/systemVerilog_prj/default_clk.sv(16)
# Time: 1990 ns Iteration: 1 Instance: /clocking_default

...............................

module clocking_default();

logic clk = 0;
always #10 clk++;

// Specify the default clocking
default clocking test @ (posedge clk);

endclocking

initial begin
$display("%0dns is current time",$time);
// Any ## is evaluated with respect to default clock
##100;
$display("%0dns is current time",$time);
$finish;
end

endmodule

 

[Robert Willy]

On Saturday, April 18, 2015 at 4:06:33 PM UTC-7, Robert Willy wrote:

Hi,

I don't know why it shows

# 1990ns is current time

for the lower part system Verilog code.


Could you explain it to me?


Thanks,



/////////////////
# 1990ns is current time
# ** Note: $finish : C:/Users/rj/Documents/systemVerilog_prj/default_clk.sv(16)
# Time: 1990 ns Iteration: 1 Instance: /clocking_default

..............................

module clocking_default();

logic clk = 0;
always #10 clk++;

When I change the ## number to 15, the second display line says 290ns.

It is even more puzzling to me now. Could you explain it to me?

Thanks


##15;

# 0ns is current time
# 290ns is current time
# ** Note: $finish : C:/Users/rj/Documents/systemVerilog_prj/default_clk.sv(16)
# Time: 290 ns Iteration: 1 Instance: /clocking_default

 

[Alan Fitch]

On 19/04/15 00:06, Robert Willy wrote:

Hi,

I don't know why it shows

# 1990ns is current time

for the lower part system Verilog code.


Could you explain it to me?

From the LRM

"The cycle delay timing control shall wait for the specified number of
clocking events. This implies that for a ##1 statement that is executed
at a simulation time that is not coincident with the associated clocking
event, the calling process shall be delayed a fraction of the associated
clock cycle."

So at time zero, the very first delay lines you up to 10 ns (the time of
the first rising edge). You then have 99 clock events left. Thus total
delay = 10 + 99 * 20 = 1990ns,

Alan

Thanks,



/////////////////
# 1990ns is current time
# ** Note: $finish : C:/Users/rj/Documents/systemVerilog_prj/default_clk.sv(16)
# Time: 1990 ns Iteration: 1 Instance: /clocking_default

..............................

module clocking_default();

logic clk = 0;
always #10 clk++;

// Specify the default clocking
default clocking test @ (posedge clk);

endclocking

initial begin
$display("%0dns is current time",$time);
// Any ## is evaluated with respect to default clock
##100;
$display("%0dns is current time",$time);
$finish;
end

endmodule

--
Alan Fitch