A Quartus problem

[talgry@yahoo.com]

Hi,
I've got an entity in my design which has an unconstrained
input/outputs.
The Quartus doesn't like it, it wants all the inputs/outputs to be
constrained.
From the instansiation of the entity the quartus can understand the
length of the vectors.

Can this problem be solved easily (without generic) ?
tnx
Tal

 

[Jim Lewis]

Tal,
Right now many synthesis tools seem to think this way.
If it is a small piece of non-registered* functionality,
I recommend that you use a procedure or function.

Setting the generic is not hard though as it is
just sig_name'length for each of your
"unconstrained" ports.

Cheers,
Jim
*registers in subprograms is something that may not be
supported by all synthesis tools (yet!).
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Hi,
I've got an entity in my design which has an unconstrained
input/outputs.
The Quartus doesn't like it, it wants all the inputs/outputs to be
constrained.
From the instansiation of the entity the quartus can understand the
length of the vectors.

Can this problem be solved easily (without generic) ?
tnx
Tal