a pipelinedesign problem in ASIP using high level synthesis

X

Xiaodong Fan

Guest
Hi!
I will look for a algorithm to design the pipeline in ASIP .The algorithms
shall operate on a set of custom instructions which
are represented as data-flow graphs and produce a resource-sharing scheme
under a given timing constraint
i.e. I have known already instruction-set and the power ,the time and the
area of each functional unit and Operation. I will assign the Operation and
functional unit to different pipelinestage to achieve optimal resource
sharing
....
have you some advice

or did the algorithm existed?
thx
 

Welcome to EDABoard.com

Sponsor

Back
Top