A loop problem which does not do what is expected...

[Tianxiang Weng]

Hi,
I have a problem that does not do what is expected.

I have several modules linked together from top to bottom. Each module has 3 error output signals: Error_O, Error_Level_O, and Error_Code_O. If a module has an error, Error_O = \'1\', Error_Level_O and Error_Code_O have their proper error info.

There are 3 arrays to correct that information from each of those modules: Error_O_m(), Error_Level_O_m(), and Error_Code_O_m(). All those arrays are confirmed to get the right values.

What I want to do is to latch the error information.

A1 : process(RESET, CLK)
variable Error_O_v : std_logic;
variable Error_Level_O_v, Error_Code_O_v : integer;

procedure INIT is
begin
Error_O <= \'0\';
Error_Level_O <= 0;
Error_Code_O <= 0;
end procedure INIT;

begin
if RESET = \'1\' then
INIT;
elsif rising_edge(CLK) then
if SINI = \'1\' then
INIT;
else
Error_O_v := \'0\';
Error_Level_O_v := 0;
Error_Code_O_v := 0;

-- propbelm may be here!
for j in 0 to G_TOP_LEVEL loop
if Error_O_v = \'0\' then
if Error_O_m(j) = \'1\' then
Error_O_v := \'1\';
Error_Level_O_v := j;
Error_Code_O_v := Error_Code_O_m(j);
end if;
end if;
end loop;

-- hope to latch error info into 3 output ports
if Error_O = \'0\' and Error_O_v = \'1\' then
Error_O <= \'1\';
Error_Level_O <= Error_Level_O_v;
Error_Code_O <= Error_Code_O_v;
end if;
end if;
end process;

During simulation, I found that 3 error signals latch nothing, keeping their initial values unchanged.

What is wrong?

Thank you.

Weng