A little bit of clarification

[parag_paul@hotmail.com]

I am implementing some debug solution for verilog signals. I need to
show drivers for a singal. Before that I wanted to clarify the
following :-
What is the difference between , procedural drivers and structural
drivers,
Are only gates structural drivers, What about Continuous assigns?
How are they different from Procedural contassign in driver treatment

Are ports someway drivers too. Arent we supposed to go into the
hieararchy and show all the drivers and not just say that there is a
driver by showing that it is a port node ???

 

[Yottameter]

If you get the list of drivers on a net, you won't see ports driving a
net. If the port is tied off at the instantiation to 1'b1, it's an
expression driving the net, not a port. Anytime you say wire
x=<something> or assign x = <something> those are drivers.

I don't know the terminology procedural drivers vs. structural. Maybe
someone else can answer.

Note that the verilog function $countdrivers will not tell you if a net
is not connected. Z's will not show up in $countdrivers, so you may have
a net connected, but it is just Z. The driver list from the PLI will
give you the complete list of drivers, even those that are Z.

The driver list (and $countdrivers) goes through ports to determine the
drivers.



parag_paul@hotmail.com wrote:

I am implementing some debug solution for verilog signals. I need to
show drivers for a singal. Before that I wanted to clarify the
following :-
What is the difference between , procedural drivers and structural
drivers,
Are only gates structural drivers, What about Continuous assigns?
How are they different from Procedural contassign in driver treatment

Are ports someway drivers too. Arent we supposed to go into the
hieararchy and show all the drivers and not just say that there is a
driver by showing that it is a port node ???

 

[Evan Lavelle]

On Mon, 24 Sep 2007 10:27:35 -0000, "parag_paul@hotmail.com"
<parag_paul@hotmail.com> wrote:

I am implementing some debug solution for verilog signals. I need to
show drivers for a singal. Before that I wanted to clarify the
following :-
What is the difference between , procedural drivers and structural
drivers,
Are only gates structural drivers, What about Continuous assigns?
How are they different from Procedural contassign in driver treatment

Are ports someway drivers too. Arent we supposed to go into the
hieararchy and show all the drivers and not just say that there is a
driver by showing that it is a port node ???

There's a lot of confusion in Verilog about what a 'driver' actually
is; the LRM basically avoids this issue (contrast with VHDL, where
drivers are central to the language, and have an obvious
correspondence with hardware).

This is my understanding, which may need correcting. In common usage,
'driver' means:

(a) continuous assignments (but *not* procedural continuous
assignments),

(b) a module input or output port (which is effectively defined as a
continuous assignment anyway), and

(c) primitive output and inout terminals (which are technically *not*
equivalent to continuous assignments).

These 3 are probably what you mean by 'structural drivers' (the LRM
says nothing about 'structural' drivers). This is basically equivalent
to a hardware view of drivers, except that port modules do not end up
as physical 'drivers'; see past threads on port coercion.

More precisely, the LRM refers to drivers in various contexts which
imply that a driver is anything which can change the value of a net,
*or* of a reg/variable. This isn't a hardware view, since much of this
stuff doesn't synthesise and has no hardware equivalent (what is a
"reg driver"?). This view now includes:

(d) The 'force' version of procedural continuous assignments, which
can be applied to nets (and both the 'force' and 'assign' procedural
continuous assignments for regs)

(e) A 'delay device', which is an obscure internal simulation object

(f) A module inout port, if you're on the inside

Note that the PLI routines aren't guaranteed to return the same
(vpiDriver) drivers in all implementations, because of net collapsing,
which rather implies that 'drivers' are not well-defined. Earlier
versions of Verilog (PLI 1.0) also apparently only identified
primitive terminals as drivers.

In short, "driver" doesn't mean very much. A more constructive way to
look at drivers may be to view a driver as anything which can schedule
an update event on the event queue.

Evan

 

[parag_paul@hotmail.com]

But there is no definition for procedural that means