A few Verilog questions

[Daku]

Although I have used Verilog in the past, it is a bit rusty now. I am
using Icarus Verilog 0.9.1.
1. How do I set signal (for example clock) pulse width, rising and
falling edge widths?
Any hints, suggestions etc., would be greatly appreciated - thanks in
advance for your help.

 

[Jonathan Bromley]

On Thu, 8 Oct 2009 19:53:37 -0700 (PDT), Daku wrote:

using Icarus Verilog 0.9.1.

Shouldn't matter. Verilog is Verilog. There may be a tiny handful
of things that Icarus doesn't fully support, but basically the
choice of simulator should be irrelevant in terms of what code
you can write.

1. How do I set signal (for example clock) pulse width, rising and
falling edge widths?

What do you mean, "set"? I can easily create a pulse of a
certain width:

reg R;
task pulse_R ( input time T );
begin
R = 1;
#T R = 0;
end
endtask

But you absolutely cannot have "edge widths". Verilog is
a digital simulation language. Simulated transitions, from
0 to 1 and back again, take place in zero time.

Perhaps you are talking about _checking_ pulse widths?
That's done using the built-in timing check functions,
within a "specify" block:

specify
$width(posedge R, 5);
// check high-level pulse on R is at least 5 units wide
endspecify

If you can be a bit more precise, we can be more helpful.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[gabor]

On Oct 8, 10:53 pm, Daku <dakup...@gmail.com> wrote:

Although I have used Verilog in the past, it is a bit rusty now. I am
using Icarus Verilog 0.9.1.
1. How do I set signal (for example clock) pulse width, rising and
falling edge widths?
Any hints, suggestions etc., would be greatly appreciated - thanks in
advance for your help.

If you mean how do you set the clock high and low time independently,
one approach is:

`timescale 1 ns / 1 ps
reg clock = 0;
always begin
#8 clock = 1; // clock low for 8 ns
#5 clock = 0; // clock high for 5 ns
end

This example uses constant time delays, but the delays
can be dynamic.

HTH,
Gabor