A difference between VHDL sources working

[toomuch]

Hi

Can someone tell me if there is a defference between the following two VHDL
sources working:
1.
process

begin

wait until C'event and C='1';

if B='0' then

Q<=B;

else

Q<= A;

end if;

end process;



2.

process

begin

if B='0' then

wait until C'event and C='1';

Q<=B;

else

wait until C'event and C='1';

Q<=A;

end if;

end process;


Simulation of this two processes gives different results. Does anybody know
why? Is there a specification discussing those cases?

Thanks for any help

 

[Marcin]

Hi,

1. You wait for rising edge on C, then sample the B signal and decide
whether to assign A or B to Q.
2. The value of B is examined at the beginning of process execution
and you choose one of the if-else branch immediately. After that you
only wait for rising edge on C to assign a value to Q.


The first will synthesize to simple flip-flop with synchronous reset
the second will synthesize to something more complex which probably is
not what you want.

Marcin

"toomuch" <toomuch@poczta.onet.pl> wrote in message news:<bsq239$sba$1@news.onet.pl>...

Hi

Can someone tell me if there is a defference between the following two VHDL
sources working:
1.
process

begin

wait until C'event and C='1';

if B='0' then

Q<=B;

else

Q<= A;

end if;

end process;



2.

process

begin

if B='0' then

wait until C'event and C='1';

Q<=B;

else

wait until C'event and C='1';

Q<=A;

end if;

end process;


Simulation of this two processes gives different results. Does anybody know
why? Is there a specification discussing those cases?

Thanks for any help