A basic doubt...

[Tia]

Here is my C code.
a = b ? N : 16 ;
for(i=0;i<a;i++)
{ statement #1;
statement #2;
}
-------------------------------------------------------
WITHOUT USING FOR LOOP, how can I code this in Verilog ?

 

[glen herrmannsfeldt]

Tia wrote:

Here is my C code.
a = b ? N : 16 ;
for(i=0;i<a;i++)
{ statement #1;
statement #2;
}
-------------------------------------------------------
WITHOUT USING FOR LOOP, how can I code this in Verilog ?

A verilog for loop, in synthesized logic, normally expands into
the appropriate number of instantiations of the contained logic.

You might put in 16 with a constant in the for loop and than
a 1 of 16 decoder with a as the input.

It might be that you really want a state machine with i as a
counter, in a register. Without knowing statement #1 and
statement #2 it is hard to say.

Do all a of them need to be evaluated each clock cycle, or just
on per clock cycle?

-- glen

 

[Tia]

inside the for loop are a set of statements that has to be executed
sequentially. I donot know whether all my statements get excuted in a
clock cycle or not. can you try to elaborate more on "You might put in
16 with a constant in the for loop and than a 1 of 16 decoder with a as
the input." ?
Thankyou so much
-Tia

 

[Jim Wu]

"Tia" <vidhu_naveen@yahoo.com> wrote in message
news:1109629915.913486.16000@z14g2000cwz.googlegroups.com...

Here is my C code.
a = b ? N : 16 ;
for(i=0;i<a;i++)
{ statement #1;
statement #2;
}
-------------------------------------------------------
WITHOUT USING FOR LOOP, how can I code this in Verilog ?

How about a "while" loop? Seriously, what exactly are you trying to do?

Jim

 

[Tia]

Jim Wu wrote:

"Tia" <vidhu_naveen@yahoo.com> wrote in message
news:1109629915.913486.16000@z14g2000cwz.googlegroups.com...
Here is my C code.
a = b ? N : 16 ;
for(i=0;i<a;i++)
{ statement #1;
statement #2;
}
-------------------------------------------------------
WITHOUT USING FOR LOOP, how can I code this in Verilog ?

How about a "while" loop? Seriously, what exactly are you trying to
do?

Jim

 

[Tia]

I want to synthesis this code without using loops.

Jim Wu wrote:

"Tia" <vidhu_naveen@yahoo.com> wrote in message
news:1109629915.913486.16000@z14g2000cwz.googlegroups.com...
Here is my C code.
a = b ? N : 16 ;
for(i=0;i<a;i++)
{ statement #1;
statement #2;
}
-------------------------------------------------------
WITHOUT USING FOR LOOP, how can I code this in Verilog ?

How about a "while" loop? Seriously, what exactly are you trying to
do?

Jim

 

[Christian Schneider]

Tia wrote:

I want to synthesis this code without using loops.

Jim Wu wrote:

"Tia" <vidhu_naveen@yahoo.com> wrote in message
news:1109629915.913486.16000@z14g2000cwz.googlegroups.com...

Here is my C code.
a = b ? N : 16 ;

should'n this be a == b in C ?? since = is a assignment == is a
comparission; but I do not see the relationship to the loop.

for(i=0;i<a;i++)
{ statement #1;
statement #2;
}

As it is in supercomputing every index in a loop can be parallelized (at
least if the size is constant ...) The hardware reflects this by
parallelizing the modules, so you will get more parallel hardware. The
code inside the loop may be sequential, that's no problem, you have a
clock, one step each clock cycle. I cannot understand why you refuse to
code a loop.

-------------------------------------------------------
WITHOUT USING FOR LOOP, how can I code this in Verilog ?

How about a "while" loop? Seriously, what exactly are you trying to

do?

Jim

 

[Jim Wu]

"Tia" <vidhu_naveen@yahoo.com> wrote in message
news:1109702602.936235.46110@z14g2000cwz.googlegroups.com...

I want to synthesis this code without using loops.

Why? Is "for" loop giving you hard time?

Jim

Jim Wu wrote:
"Tia" <vidhu_naveen@yahoo.com> wrote in message
news:1109629915.913486.16000@z14g2000cwz.googlegroups.com...
Here is my C code.
a = b ? N : 16 ;
for(i=0;i<a;i++)
{ statement #1;
statement #2;
}
-------------------------------------------------------
WITHOUT USING FOR LOOP, how can I code this in Verilog ?

How about a "while" loop? Seriously, what exactly are you trying to
do?

Jim

 

[Neo]

yeah, also you can try by putting in each assignment seperately instead
of a loop.