{a,b} lsb-msb or msb-lsb ?

N

nyffeler

Guest
Sorry this is a beginner question.

Is it true that in concatenation {a,b} a is lsb and b is msb,
but binay representation 2'bxx starts with msb?

At least I have the feeling that the following case is treated like this.

module gaga (clk, trigger, ready, error);
input clk, trigger,ready;
output error;
reg status;

always @(posedge clk)
begin
case ({trigger,ready})
2'b11: status=0; //ready = error false
2'b10: status=1; //not ready = error true
default: status = error
endcase
end
assign error = status;
endmodule
 
nyffeler wrote:
Sorry this is a beginner question.

Is it true that in concatenation {a,b} a is lsb and b is msb,
but binay representation 2'bxx starts with msb?

At least I have the feeling that the following case is treated like this.

module gaga (clk, trigger, ready, error);
input clk, trigger,ready;
output error;
reg status;

always @(posedge clk)
begin
case ({trigger,ready})
2'b11: status=0; //ready = error false
2'b10: status=1; //not ready = error true
default: status = error
endcase
end
assign error = status;
endmodule
No, in the concatenation {a,b} a is the MSB.
 
"nyffeler" <nyffeler@phys.chem.ethz.ch> wrote in message
news:43f207a6$1@news1.ethz.ch...
Sorry this is a beginner question.

Is it true that in concatenation {a,b} a is lsb and b is msb,
but binay representation 2'bxx starts with msb?

At least I have the feeling that the following case is treated like this.

module gaga (clk, trigger, ready, error);
input clk, trigger,ready;
output error;
reg status;

always @(posedge clk)
begin
case ({trigger,ready})
2'b11: status=0; //ready = error false
2'b10: status=1; //not ready = error true
default: status = error
endcase
end
assign error = status;
endmodule
A little elaboration is, perhaps, in order:

The Verilog vectors are left-to-right orientation. Two numbering schemes
are available, High-to-Low (typically seen in most Verilog code) and
Low-to-High: first[5:0] or second[0:5]. If you're using the second form,
you may consider bit 5 to be the "msbit" but it's not. The MSbit is always
the leftmost bit, whichever numbering scheme is used. The addition of
first[5:0]+second[0:5] will give a result where the rightmost bit - the
LSbit - is first[0]^second[5] and the carry out to the next stage is
first[0]&second[5].

The concatenation of {a,b} gives the leftmost bit of vector "a" in the
leftmost bit of the result (which should be considered the MSbit in both
cases) and the rightmost bit of vector "b" is the rightmost bit of the
result: the LSbit.
 
In article <q1pIf.101$kg.10@news02.roc.ny>, "John_H" <johnhandwork@mail.com> wrote:
"nyffeler" <nyffeler@phys.chem.ethz.ch> wrote in message
news:43f207a6$1@news1.ethz.ch...
Sorry this is a beginner question.

Is it true that in concatenation {a,b} a is lsb and b is msb,
but binay representation 2'bxx starts with msb?

At least I have the feeling that the following case is treated like this.

module gaga (clk, trigger, ready, error);
input clk, trigger,ready;
output error;
reg status;

always @(posedge clk)
begin
case ({trigger,ready})
2'b11: status=0; //ready = error false
2'b10: status=1; //not ready = error true
default: status = error
endcase
end
assign error = status;
endmodule

A little elaboration is, perhaps, in order:

The Verilog vectors are left-to-right orientation. Two numbering schemes
are available, High-to-Low (typically seen in most Verilog code) and
Low-to-High: first[5:0] or second[0:5]. If you're using the second form,
you may consider bit 5 to be the "msbit" but it's not. The MSbit is always
the leftmost bit, whichever numbering scheme is used. The addition of
first[5:0]+second[0:5] will give a result where the rightmost bit - the
LSbit - is first[0]^second[5] and the carry out to the next stage is
first[0]&second[5].

The concatenation of {a,b} gives the leftmost bit of vector "a" in the
leftmost bit of the result (which should be considered the MSbit in both
cases) and the rightmost bit of vector "b" is the rightmost bit of the
result: the LSbit.
Thank you for helping me.
 

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