80c186 and transparent latch?

[Mook Johnson]

I'm working on a design that uses an 80c186 with external memory and rom.

While diagnosing i realized something that is strange to an analog inclined
person like myself. The bus is multiplexed using a transparent latch which
makes the the outputs follow the inputs while the LE is high (transparent
part) and latched in the falling edge. (old 373 chip). What I didn't
expect to see was that the AD signals change while the 80c186 ALE is high
and therefore cause glitches on the output of the latch (address bus). The
system works because the setup and hold times for the memories are not
violeted before the read/reite signals are asserted, but it would seem to
add to the EMI produced by the memory bus. This would be solved if the
address was only latched on the negative edge without the transparerent part
when LE is high.

Am I missing something here?

 

[Tam/WB2TT]

"Mook Johnson" <mook@mook.net> wrote in message
news:nE1Qe.8$Nx.5@tornado.texas.rr.com...

I'm working on a design that uses an 80c186 with external memory and rom.

While diagnosing i realized something that is strange to an analog
inclined person like myself. The bus is multiplexed using a transparent
latch which makes the the outputs follow the inputs while the LE is high
(transparent part) and latched in the falling edge. (old 373 chip). What
I didn't expect to see was that the AD signals change while the 80c186 ALE
is high and therefore cause glitches on the output of the latch (address
bus). The system works because the setup and hold times for the memories
are not violeted before the read/reite signals are asserted, but it would
seem to add to the EMI produced by the memory bus. This would be solved
if the address was only latched on the negative edge without the
transparerent part when LE is high.

Am I missing something here?

Sort of. The way it is set up gives you the most address setup time. That

is, address on the buffered bus is valid long before the falling edge of
ALE. Keep in mind, though, that when the original 186 came out, memory was
slow. By using an edge triggered latch, you are also changing the address to
READ and WR times.

BTW, congratulations for using a 373 and not the stupid Intel part. I would
use the HCT, though.

Tam

Tam

 

[Mook Johnson]

Thanks I knew there had to be a reason.

The word "tranparent" was lost on me and I thought the latch was bad because
the output was changing "before" the falling edge Turned out this is
correct behavior but lead to this topic as to why this is desirable.

thanks again


"Tam/WB2TT" <t-tammaru@c0mca$t.net> wrote in message
news:XMydnVNR49HOIY3eRVn-hQ@comcast.com...

"Mook Johnson" <mook@mook.net> wrote in message
news:nE1Qe.8$Nx.5@tornado.texas.rr.com...
I'm working on a design that uses an 80c186 with external memory and rom.

While diagnosing i realized something that is strange to an analog
inclined person like myself. The bus is multiplexed using a transparent
latch which makes the the outputs follow the inputs while the LE is high
(transparent part) and latched in the falling edge. (old 373 chip).
What I didn't expect to see was that the AD signals change while the
80c186 ALE is high and therefore cause glitches on the output of the
latch (address bus). The system works because the setup and hold times
for the memories are not violeted before the read/reite signals are
asserted, but it would seem to add to the EMI produced by the memory bus.
This would be solved if the address was only latched on the negative edge
without the transparerent part when LE is high.

Am I missing something here?

Sort of. The way it is set up gives you the most address setup time. That
is, address on the buffered bus is valid long before the falling edge of
ALE. Keep in mind, though, that when the original 186 came out, memory was
slow. By using an edge triggered latch, you are also changing the address
to READ and WR times.

BTW, congratulations for using a 373 and not the stupid Intel part. I
would use the HCT, though.

Tam

Tam