8 ch countdown timer - doable in a CPLD?

[Richard Cooke]

Hello,

I'm new to the world of CPLDs or FPGAs so please be easy on me. We
have a requirement for an 8 channel (12 channel would be better)
countdown timer at 12 to 14 bit resolution with a 20MHz clock input.

All we need is to be able to load the channel's timer value via the
processor's data bus and start the timers after the last channel is
loaded. We need 8 (or 12) outputs that go high during the countdown
and turns off when the timer times out and stays off until the next
time they are loaded.

Is this possible in a relatively cheap CPLD and which "family" would
be a good starting point? If this is a complicated design we would
certainly entertain the possibility of farming this out.

Thanks,

Richard

 

[John_H]

I'd recommend contacting your Altera rep to find out if the MaxPlus-II
devices are available for you. For your application, these chips could be
the cheapest way to go. Normally a CPLD in >> 128 macrocells won't be
extremely inexpensive. Not bad, but not the savings you can achieve. The
MaxPlus-II devices are like tiny, old-generation FPGAs with embedded flash
memory giving you full functionality without external boot memories.

The no-frills architecture (who needs PLLS or RAM for your application?)
fits with no-frill requirements.

If these relatively new devices are available, they may be the most
cost-effective way to go.


"Richard Cooke" <rcooke_@symbolgoeshere_redmtnengr.com> wrote in message
news:9i5cd0ht0rc0u76htnkc78dguklrm700jk@4ax.com...

Hello,

I'm new to the world of CPLDs or FPGAs so please be easy on me. We
have a requirement for an 8 channel (12 channel would be better)
countdown timer at 12 to 14 bit resolution with a 20MHz clock input.

All we need is to be able to load the channel's timer value via the
processor's data bus and start the timers after the last channel is
loaded. We need 8 (or 12) outputs that go high during the countdown
and turns off when the timer times out and stays off until the next
time they are loaded.

Is this possible in a relatively cheap CPLD and which "family" would
be a good starting point? If this is a complicated design we would
certainly entertain the possibility of farming this out.

Thanks,

Richard