8 bit adder

Hi,
I am a newbie to VHDL and trying to implement an 8 bit adder. I can get
a 4 bit adder to work with almost similar code. But when I extend it
to 8 bits, it does not work properly. Any ideas what I could be doing
wrong here?

This is the 4 bit adder which works

-- a0 36 FLEX DIP switch 5
-- a1 35 FLEX DIP switch 6
-- a2 34 FLEX DIP switch 7
-- a3 33 FLEX DIP switch 8
-- b0 41 FLEX DIP switch 1
-- b1 40 FLEX DIP switch 2
-- b2 39 FLEX DIP switch 3
-- b3 38 FLEX DIP switch 4

library IEEE;
use IEEE.std_logic_1164.all;

entity full_adder is
port ( a,b,cin : in std_logic;
sum,cout: out std_logic );
end entity;

architecture behavior of full_adder is
begin
sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end;

library IEEE;
use IEEE.std_logic_1164.all;
entity four_bit_adder is
port ( a, b : in std_logic_vector(3 downto 0);
--a, b : in std_logic_vector(7 downto 0);
cin: in std_logic :='0';
sum : buffer std_logic_vector(3 downto 0);
--sum : buffer std_logic_vector(7 downto 0);
cout : out std_logic;
seven_seg1: out std_logic_vector(6 downto 0)
--seven_seg2: out std_logic_vector(6 downto 0)
);
end ;

--instantiate 1 bit full adder
architecture structural of four_bit_adder is
signal c1,c2,c3 : std_logic;
--c4,c5,c6,c7
component full_adder port(
a,b,cin : in std_logic;
sum,cout: out std_logic);
end component;

begin
FA0: full_adder port map(a(0),b(0),cin,sum(0),c1);
FA1: full_adder port map(a(1),b(1),c1,sum(1),c2);
FA2: full_adder port map(a(2),b(2),c2,sum(2),c3);
FA3: full_adder port map(a(3),b(3),c3,sum(3),cout);
-- FA3: full_adder port map(a(3),b(3),cin,sum(3),c4);

-- FA4: full_adder port map(a(4),b(4),cin,sum(4),c5);
-- FA5: full_adder port map(a(5),b(5),cin,sum(5),c6);
-- FA6: full_adder port map(a(6),b(6),cin,sum(6),c7);
-- FA7: full_adder port map(a(7),b(7),cin,sum(7),cout);



--choose 4 bits of sum variable each time
with sum(3 downto 0) select
seven_seg1 <= "1000000" when "0000", -- 0
"1111001" when "0001", -- 1
"0100100" when "0010", -- 2
"0110000" when "0011", -- 3
"0011001" when "0100", -- 4
"0010010" when "0101", -- 5
"0000010" when "0110", -- 6
"1111000" when "0111", -- 7
"0000000" when "1000", -- 8
"0010000" when "1001", -- 9
"0001000" when "1010", -- A
"0000011" when "1011", -- b
"1000110" when "1100", -- C
"0100001" when "1101", -- d
"0000110" when "1110", -- E
"0001110" when "1111", -- F
"1111111" when others; -- all off

--with sum (7 downto 4) select
--seven_seg2 <= "0000001" when "0000", -- 0
-- "1001111" when "0001", -- 1
-- "0010010" when "0010", -- 2
-- "0000110" when "0011", -- 3
-- "1001100" when "0100", -- 4
-- "0100100" when "0101", -- 5
-- "0100000" when "0110", -- 6
-- "0001111" when "0111", -- 7
-- "0000000" when "1000", -- 8
-- "0000100" when "1001", -- 9
-- "0001000" when "1010", -- A
-- "1100000" when "1011", -- b
-- "0110001" when "1100", -- C
-- "1000010" when "1101", -- d
-- "0110000" when "1110", -- E
-- "0111000" when "1111", -- F
-- "1111111" when others; -- all off

end architecture structural; -- of 4bitadder

but if uncomment some of the lines of code to make it work for 8 bit
adder,it does not work.


Thanks,
Jatinder

 

[Ralf Hildebrandt]

jatinder.dua@gmail.com wrote:

I am a newbie to VHDL and trying to implement an 8 bit adder.

Hmm ... if it is a class assignment to you, that forces you to use
fulladder cells and connect them to a chain, it is ok. If you try to
write useable VHDL there is a _much_ easier and more flexible solution.

I can get
a 4 bit adder to work with almost similar code. But when I extend it
to 8 bits, it does not work properly. Any ideas what I could be doing
wrong here?
....
FA3: full_adder port map(a(3),b(3),c3,sum(3),cout);
-- FA3: full_adder port map(a(3),b(3),cin,sum(3),c4);
....
but if uncomment some of the lines of code to make it work for 8 bit
adder,it does not work.

Compare the two lines. There is a difference for the carry-in! Use c3
and not cin for the commented FA3.


Ralf

 

[krby_xtrm]

if your not critical with carry_out....
you could use:

a,b : in std_logic_vector (7 downto 0);
....
signal c : out std_logic_vector (7 downto 0);

c <= a + b;

....

 

[Ralf Hildebrandt]

krby_xtrm wrote:

if your not critical with carry_out....
you could use:

a,b : in std_logic_vector (7 downto 0);
...
signal c : out std_logic_vector (7 downto 0);

c <= a + b;

No, because no arithmetics are defined on std_(u)logic_vectors - and
they should not as done in std_logic_arith. Use numeric_std instead and
use signed / unsigned for this propose

Ralf

 

[Ralf Hildebrandt]

Ralf Hildebrandt wrote:

Use numeric_std instead and
use signed / unsigned for this propose

"... for this purpose."

Ralf

 

[krby_xtrm]

my mistake, you can use integer instead...

 

[krby_xtrm]

use.std_logic_unsiged.all

with that it is possible to add up std_logic types

 

[Ralf Hildebrandt]

krby_xtrm wrote:

use.std_logic_unsiged.all

with that it is possible to add up std_logic types

Yes - possible, but _not_ recommended. Don't do arithmetics on
std_(u)logic-vectors! You limit yourself to eigther signed or to
unsigned (as with std_logic_unsigned) or the behavior is undefined.

constant sig_a : std_ulogic_vector(7 downto 0):="11111111";
constant sig_b : std_ulogic_vector(7 downto 0):="00010000";

....
if (sig_a > sig_b) then
....

What do you expect? If sig_a is threatened signed, it is -1 and
therefore lower than sig_b. If it is unsigned, it is 255 and therefore
bigger.

-> Use IEEE.numeric_std.ALL! Use the types unsigned or signed, if you
need vector types. You may also use integers, but there are some
limitations (e.g. 32 bit width). Numeric_std is a standard library - the
others are not - even, if their names sound so.

Ralf