74ls193 in coolrunner

[Fredk]

HI All,

Was wondering if someone could point me in the right direction on a
couple of problems?

I am using webpack 4.1 and trying to create a 74ls193. I first basically
built it from scratch using the logic diagram from the TTL datasheet but it
would not work correctly in a circuit.

Looking at the counters in the xilinx library there is none that clock
using the UP or Down like the ls193. They all use up/down pins and then
clock with a seperate pin.

Anyone have a solution or idea of how I could design a ls193 with either
descrete logic (like I tried) or using the library counters?

I am not a student and I am just doing this for fun and to learn a bit.
I have successfully made other TTl chips work (not included in the library)
like a 74ls670 (I built this one all discreet also in webpack)

I am not looking for someone to hold my hand (although I am a newbee to
webpack and xilinx devices), but maybe someone that has done this before (
made a ls193 or similiar) and could point me in the right direction.

Thanks,

Fred

 

[Hal Murray]

I am using webpack 4.1 and trying to create a 74ls193. I first basically
built it from scratch using the logic diagram from the TTL datasheet but it
would not work correctly in a circuit.

Anyone have a solution or idea of how I could design a ls193 with either
descrete logic (like I tried) or using the library counters?

The party line is don't-do-that, Do something else, for example use
a different part.

The basic rule is that you have to meet both setup and
hold times on all flip-flops in your design. That gets tricky
if you have a complicated clock distribution system.

Xilinx FPGAs have a very low skew clock distribution system. They
promise that the hold time will be 0. (or really that the min prop
time will be enough to cover the hold time) That means you only
have to worry about the setup time. Their software is smart enough
to figure that out and tell you the max speed your design will
run at.

Where are your up/down pulses coming from? If they come out of
a state machine (flip-flop), then you want to use the same clock
that drives that state machine to drive a counter, and use the
up/down signals to decide if your counter goes up, down, hold...

It will all make sense after you get used to it. It's much
cleaner/simpler for high speed designs.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Fredk]

I guess I need to read as much as I can to try and understand the FF's
in xilinx.......as even using there library counter I can't get a 193's
equiv. to work in a circuit designed for a 74ls193.

Fred




"Hal Murray" <hmurray@suespammers.org> wrote in message
news:102vrnvnm16debb@corp.supernews.com...

I am using webpack 4.1 and trying to create a 74ls193. I first
basically
built it from scratch using the logic diagram from the TTL datasheet but
it
would not work correctly in a circuit.

Anyone have a solution or idea of how I could design a ls193 with
either
descrete logic (like I tried) or using the library counters?

The party line is don't-do-that, Do something else, for example use
a different part.

The basic rule is that you have to meet both setup and
hold times on all flip-flops in your design. That gets tricky
if you have a complicated clock distribution system.

Xilinx FPGAs have a very low skew clock distribution system. They
promise that the hold time will be 0. (or really that the min prop
time will be enough to cover the hold time) That means you only
have to worry about the setup time. Their software is smart enough
to figure that out and tell you the max speed your design will
run at.

Where are your up/down pulses coming from? If they come out of
a state machine (flip-flop), then you want to use the same clock
that drives that state machine to drive a counter, and use the
up/down signals to decide if your counter goes up, down, hold...

It will all make sense after you get used to it. It's much
cleaner/simpler for high speed designs.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or
unsolicited
commercial e-mail to my suespammers.org address or any of my other
addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Peter Alfke]

Don't treat the 7400 series as gospel.
Those TTL-MSI circuits were defined with two constraints:
1.
make them universal, so that only a limiyted number of different
circuits needs to be built,
2.
and fit them in a 16-pin apckage, without giving up the ability to expand.

That was the rationale behind all those circuits (I know, I was there at
the creation).
Using the same constraints when implementing such functions in an FPGA
does not make any sense at all.
Peter Alfke
--------------------------------
Hal Murray wrote:

I am using webpack 4.1 and trying to create a 74ls193. I first basically
built it from scratch using the logic diagram from the TTL datasheet but it
would not work correctly in a circuit.

Anyone have a solution or idea of how I could design a ls193 with either
descrete logic (like I tried) or using the library counters?

The party line is don't-do-that, Do something else, for example use
a different part.

The basic rule is that you have to meet both setup and
hold times on all flip-flops in your design. That gets tricky
if you have a complicated clock distribution system.

Xilinx FPGAs have a very low skew clock distribution system. They
promise that the hold time will be 0. (or really that the min prop
time will be enough to cover the hold time) That means you only
have to worry about the setup time. Their software is smart enough
to figure that out and tell you the max speed your design will
run at.

Where are your up/down pulses coming from? If they come out of
a state machine (flip-flop), then you want to use the same clock
that drives that state machine to drive a counter, and use the
up/down signals to decide if your counter goes up, down, hold...

It will all make sense after you get used to it. It's much
cleaner/simpler for high speed designs.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Fredk]

Peter,

I see your point exactly, but for the sake of testing I want to make
sure a suitable ls193 replacement works. I am only making one ttl chip at a
time and placing it in a working circuit comprised of many ttl chips. I have
done this with a ls670 I built in xilinx and a ls191. Which have both worked
fine in circuit.

I plan to slowly implement all the other ttl components until its all on
a single cpld.

An argument for placing everything on the cpdl at once is probably
justified, but I am a newbee and would like to take it in steps to make sure
that the individual parts work correctly before trying to debug something
very large. I feel that when all the parts work then I can adjust the whole
design to better fit or work in a cpld.

Again I am new to this (cpld) so I may have an old style rational.

Thanks,

Fred

"Peter Alfke" <peter@xilinx.com> wrote in message
news:40312592.890CC95A@xilinx.com...

Don't treat the 7400 series as gospel.
Those TTL-MSI circuits were defined with two constraints:
1.
make them universal, so that only a limiyted number of different
circuits needs to be built,
2.
and fit them in a 16-pin apckage, without giving up the ability to expand.

That was the rationale behind all those circuits (I know, I was there at
the creation).
Using the same constraints when implementing such functions in an FPGA
does not make any sense at all.
Peter Alfke
--------------------------------
Hal Murray wrote:

I am using webpack 4.1 and trying to create a 74ls193. I first
basically
built it from scratch using the logic diagram from the TTL datasheet
but it
would not work correctly in a circuit.

Anyone have a solution or idea of how I could design a ls193 with
either
descrete logic (like I tried) or using the library counters?

The party line is don't-do-that, Do something else, for example use
a different part.

The basic rule is that you have to meet both setup and
hold times on all flip-flops in your design. That gets tricky
if you have a complicated clock distribution system.

Xilinx FPGAs have a very low skew clock distribution system. They
promise that the hold time will be 0. (or really that the min prop
time will be enough to cover the hold time) That means you only
have to worry about the setup time. Their software is smart enough
to figure that out and tell you the max speed your design will
run at.

Where are your up/down pulses coming from? If they come out of
a state machine (flip-flop), then you want to use the same clock
that drives that state machine to drive a counter, and use the
up/down signals to decide if your counter goes up, down, hold...

It will all make sense after you get used to it. It's much
cleaner/simpler for high speed designs.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or
unsolicited
commercial e-mail to my suespammers.org address or any of my other
addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Jim Granville]

Fredk wrote:

Peter,

I see your point exactly, but for the sake of testing I want to make
sure a suitable ls193 replacement works. I am only making one ttl chip at a
time and placing it in a working circuit comprised of many ttl chips. I have
done this with a ls670 I built in xilinx and a ls191. Which have both worked
fine in circuit.

I plan to slowly implement all the other ttl components until its all on
a single cpld.

That's impressive patience, but it is a proven-safe pathway.

An argument for placing everything on the cpdl at once is probably
justified, but I am a newbee and would like to take it in steps to make sure
that the individual parts work correctly before trying to debug something
very large. I feel that when all the parts work then I can adjust the whole
design to better fit or work in a cpld.

Understood.

Again I am new to this (cpld) so I may have an old style rational.

Taking a close look at the '193, it CAN be implemented in a CPLD, but
not in a natural/efficent way.

I see two choices :
a) Keep with your method, but when you strike a device like a '193,
try and change it to TWO TTL devices, a GATE and a Sync counter '161 series
You can verify the new combination, and also easily replace it with a
CPLD.

b) If you _must_ duplicate the '193, you will need to create what they
do, to merge clocks. ( peek at the Fairchild 74F193 data )
This needs a cross-coupled latch, to set DIRECTION on the Falling
Edge, and an AND gate to merge the two clocks.
Note the '193 requires that the inactive clock is HIGH, and has min
pulse widths on dirn change that are > same direction.

-jg

 

[Jim Granville]

Jim Granville wrote:
<snip>

b) If you _must_ duplicate the '193, you will need to create what they
do, to merge clocks. ( peek at the Fairchild 74F193 data )
This needs a cross-coupled latch, to set DIRECTION on the Falling Edge,
and an AND gate to merge the two clocks.
Note the '193 requires that the inactive clock is HIGH, and has min
pulse widths on dirn change that are > same direction.

To show your request was not unreasonable, I should have added that
I actually did this in a 22V10 a while ago, for
an 'electronic thumbwheel', where you have UP and DOWN buttons above
and below a 7 segment display.
-jg

 

[Fredk]

Jim,

Thanks for the input on this... I have started to make a JK flip flop
with set and clear to see if I can make it work

Fred

"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:5qbYb.24594$ws.3031929@news02.tsnz.net...

Jim Granville wrote:
snip
b) If you _must_ duplicate the '193, you will need to create what they
do, to merge clocks. ( peek at the Fairchild 74F193 data )
This needs a cross-coupled latch, to set DIRECTION on the Falling Edge,
and an AND gate to merge the two clocks.
Note the '193 requires that the inactive clock is HIGH, and has min
pulse widths on dirn change that are > same direction.

To show your request was not unreasonable, I should have added that
I actually did this in a 22V10 a while ago, for
an 'electronic thumbwheel', where you have UP and DOWN buttons above
and below a 7 segment display.
-jg