74ATC Series Logic Interface

[Mark]

I updating an old design to interface a "Legacy" A/D converter. I have a
12 bit parallel out A/D with TTL type output levels. A min logic 1 is
2.4 volts and the max logic zero is 0.4 volts. I want to interface this
to an all CMOS system so I'm looking at using a 74ACT buffer between the
A/D and the rest of the system (TTL inputs, CMOS Outputs).

Dururing the conversion process the A/D outputs go Tri-State (High -Z).

This will cause the inputs of the 74ACT part to "float" during this time.

So my question is: Is it OK the float 74ACT inputs. If floated, what
state do they settle to? Do I need pull-ups (or pull-downs) for
reliable operation?

Thanks,

Mark

 

[@com.aol(reverse)]

Mark wrote:

So my question is: Is it OK the float 74ACT inputs. If floated, what
state do they settle to? Do I need pull-ups (or pull-downs) for
reliable operation?

Though devices have gotten more user-friendly over the years, and some
manufacturers now include things like weak pullups in certain logic
lines, it's still considered bad practice to allow unused CMOS to float.
Everything depends on the exact chip design of course, but in many
families CMOS inputs left in an undefined state can float toward a point
where both the high-side and low-side devices can turn on at the same
time. This is bad.

Unless you know your exact vendor and how his chips handle floating
inputs (and you know that you'll never use a different brand), it's
always a good idea to use some pullup. On the plus side, CMOS doesn't
need much bias current, a 100K resistor will work just fine.

This also gives the added advantage of defining the input when the input
tri-states.

- Steve

 

[John Larkin]

On Mon, 15 Mar 2004 11:15:19 -0500, Mark <marketmark@onebox.com>
wrote:

I updating an old design to interface a "Legacy" A/D converter. I have a
12 bit parallel out A/D with TTL type output levels. A min logic 1 is
2.4 volts and the max logic zero is 0.4 volts. I want to interface this
to an all CMOS system so I'm looking at using a 74ACT buffer between the
A/D and the rest of the system (TTL inputs, CMOS Outputs).

Dururing the conversion process the A/D outputs go Tri-State (High -Z).

This will cause the inputs of the 74ACT part to "float" during this time.

So my question is: Is it OK the float 74ACT inputs. If floated, what
state do they settle to?

They probably just stay put for quite some time. How long might the
tristate condition last?

Do I need pull-ups (or pull-downs) for
reliable operation?

Not really. In theory an input may eventually drift into its linear
range and use a bit more power, but even that won't do any harm.

John