T
Tobias Weingartner
Guest
Hello all,
I'm trying to figure out how you would use an 74act297 (or similar)
along with a 74ls393 to implement a circuit that would have the
following properties:
f_in in the range of 60Hz to 4800Hz.
f_out in the range of 16*f_in.
So if I understand this correctly, I'm setting N=16 (1/2 of the '393).
The f_c would be calculated as follows (am I right here?):
f_c = ((16*4800Hz - 16*60Hz) / 2) + 16*60Hz) = 38940Hz
If the above is right, the I/D_CLK can then be figured out using:
I/D_CLK = f_c * 2N = 38940 * 2(16) = 1246080Hz
If I'm still on track, and I want to have minimum ripple in the output
of this circuit, I'd be looking at setting K>M/4. If I set the K_CLK
to be the same as I/D_CLK, then M = 32. Which means that we'd like to
have K >= 8. Pretty much anything but having the K counter inhibited
will do this. Let's assume we set K = 16 (or 2^4).
To calculate the df_max we do:
df_max = (f_out)_max - f_c = Mf_c/2KN = 32(38940)/2(16)16 =
38940/16 = 2433Hz.
Looking at the design specs, we see(f_out)_max is 4800*16 = 76800Hz,
and f_c = 38940Hz, so df_max should really be something like
df_max = 76800Hz - 38940Hz = 36960Hz. Seems we are quite a bit short.
I assume that I can increase this by raising M. However, raising M
means we have to raise K... Which means raising M, which means...
Well, you get the point.
Is it even possible to design a ADPLL that will lock onto a signal
in the range of 60Hz - 4800Hz, and produce something in-phase, with
minimal ripple in the range 16 times the input frequency?
I'm sure I'm missig something...
--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax
I'm trying to figure out how you would use an 74act297 (or similar)
along with a 74ls393 to implement a circuit that would have the
following properties:
f_in in the range of 60Hz to 4800Hz.
f_out in the range of 16*f_in.
So if I understand this correctly, I'm setting N=16 (1/2 of the '393).
The f_c would be calculated as follows (am I right here?):
f_c = ((16*4800Hz - 16*60Hz) / 2) + 16*60Hz) = 38940Hz
If the above is right, the I/D_CLK can then be figured out using:
I/D_CLK = f_c * 2N = 38940 * 2(16) = 1246080Hz
If I'm still on track, and I want to have minimum ripple in the output
of this circuit, I'd be looking at setting K>M/4. If I set the K_CLK
to be the same as I/D_CLK, then M = 32. Which means that we'd like to
have K >= 8. Pretty much anything but having the K counter inhibited
will do this. Let's assume we set K = 16 (or 2^4).
To calculate the df_max we do:
df_max = (f_out)_max - f_c = Mf_c/2KN = 32(38940)/2(16)16 =
38940/16 = 2433Hz.
Looking at the design specs, we see(f_out)_max is 4800*16 = 76800Hz,
and f_c = 38940Hz, so df_max should really be something like
df_max = 76800Hz - 38940Hz = 36960Hz. Seems we are quite a bit short.
I assume that I can increase this by raising M. However, raising M
means we have to raise K... Which means raising M, which means...
Well, you get the point.
Is it even possible to design a ADPLL that will lock onto a signal
in the range of 60Hz - 4800Hz, and produce something in-phase, with
minimal ripple in the range 16 times the input frequency?
I'm sure I'm missig something...
--
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax