7493 counters

[GLMVSTOTT]

Why does my counter reset to 1 instead of zero? What can I do about it? We are
trying to make it count from 0 to 4 and rest on 5.

 

[CFoley1064]

Subject: 7493 counters
From: glmvstott@aol.com (GLMVSTOTT)
Date: 3/20/2004 5:58 AM Central Standard Time
Message-id: <20040320065855.08963.00001653@mb-m14.aol.com

Why does my counter reset to 1 instead of zero? What can I do about it? We
are
trying to make it count from 0 to 4 and rest on 5.

Lucky day for you. Most homework questions don't get much of a response.

The first thing you need to do is really look at the data sheet, and make sure
you understand it. The 7493 has oddball pinouts -- make absolutely sure you've
got Vcc (pin 5) and GND (pin 10) right. The 7493 is a divide-by-2 and
divide-by-eight counter. The internals of the IC can be represented by 4
toggle flip-flops (clock input causes the Q output to toggle), which actually
makes them individual divide-by-2 counters. The internals can be represented
like this (use fixed font or M$ Notepad):

7493 Divide-by Two/Divide-by-Eight Counter IC
CP1 o--------------------.
.------. | .------. .------. .------.
| T | | | T | | T | | T |
| 0 | | | 1 | | 2 | | 3 |
CP0 o----o Qo----. '--o Qo--o--o Qo-o--o Qo--.
|CP' | | |CP' | | |CP' | | |CP' | |
| | | | | | | | | | | |
| CLR | | | CLR | | | CLR | | | CLR | |
'--o---' | '--o---' | '--o---' | '--o---' |
| | | | | | | |
.--o--------|---------o------|-----o-----|-----' |
| | | | |
,-O-. | | | |
| & | | | | |
'---' | | | |
| | | | | |
o o o o o o
MR1 MR2 Q0 Q1 Q2 Q3

MR1 and MR2 both have to be logic 1 to trigger the CP' (reset), which works for
all 4 T FFs. Since you want a divide-by-5, your circuit could look like this:

7493 as Divide-by-5 Counter
..-------------------------------------.
| |
| | F(in)
| CP0 o------o
| 7493 |
| |
| CP1 o--.
| | |
| MR2 MR1 Q3 Q2 Q1 Q0 | |
'---o-----o---------o---o---o---o-----' |
| | | | |
| '-------------|-------o--------'
| |
'-------------------o
|
|
F(out) (Divide-by-5)o

Notice how you've folded the output of the first FF T0 into the clock of the
second. By plugging the Q0 and Q2 outputs into the two MR inputs, the chip
will count 0, 1, 2, 3, 4, and then will almost instantaneously reset when both
Q0 and Q2 are high, resulting in a divide-by five you can pick off at the Q2
output. Or you can have a binary divide-by-5 with Q0 (LSB), Q1 and Q2 (MSB).
Since the 7493 is an asynchronous ripple counter, you have to beware glitches
on ns transitions between counts. You haven't given any decription of usage on
your post, so it may be possible you're catching a ripple transition or the
next clock if you're clocking on the same clock as the 7493. Remember that the
7493 changes state on the + to - transition of the clock. You'll want to
acquire the data on a - to + transition, otherwise you might get bad data (the
chip is doing exactly what you've wired it to do, not what you want it to do).

Now for your question. Always assume you either don't understand what the chip
does (RTFDS -- Read The Data Sheet), or that you've wired it wrong first. Once
you're *sure* your head isn't wired wrong and your circuit isn't wired wrong,
look at your signals. If you're not using clean, debounced, noise free
signals, you can have unexpected results. Beware long wiring runs and
crosstalk (especially if you're using high-impedance inputs like the
74HC/HC/*C*/93). Pullup/pulldown resistors can help here.

This stuff is the easy part (believe it or not). Homework questions generally
get a very poor (and sometimes mildly hostile) response on the newsgroups.

Good luck
Chris