64-bit wide multiple port instances

[Jake]

Hi,

Let me start off by saying that I am a custom circuit designer, so my
knowledge of Verilog is very barebones.

For each of my custom circuits, I'm writing Verilog code. A lot of
times, a port coming into a circuit will be several bits wide. To
represent the fact that this is an analog signal, in the code, I
represent each signal coming into the port as a 64-bit bus. An
example is shown below:

input [63:0] inputPort [9:0];

I'm doing all of this in Cadence, using NC-Verilog as my compiler.
When I close out each individual file, I don't get any compilation
errors, i.e., it seems to be happy with the syntax I'm using above.
However, when I compile the entire design and try to simulate, it
chokes on this syntax (asking for a semi-colon after 'inputPort'),
suggesting to me that multidimensional arrays are not being
supported. Has anyone else seen a problem like this?

Thanks,
Jake

 

[John_H]

Multi-dimensional ports are simply not supported in Verilog2001. The
closest you *might* get is the use of predefined interfaces in SystemVerilog
but I would doubt that would work as well. It's been desirable in the past
to have 2-D ports but they just aren't supported in the language. Using one
large 1-D port that takes a concatenation of the individual ports is a
workaround.


"Jake" <wegman.jake@gmail.com> wrote in message
news:1189539232.085188.312220@v29g2000prd.googlegroups.com...

Hi,

Let me start off by saying that I am a custom circuit designer, so my
knowledge of Verilog is very barebones.

For each of my custom circuits, I'm writing Verilog code. A lot of
times, a port coming into a circuit will be several bits wide. To
represent the fact that this is an analog signal, in the code, I
represent each signal coming into the port as a 64-bit bus. An
example is shown below:

input [63:0] inputPort [9:0];

I'm doing all of this in Cadence, using NC-Verilog as my compiler.
When I close out each individual file, I don't get any compilation
errors, i.e., it seems to be happy with the syntax I'm using above.
However, when I compile the entire design and try to simulate, it
chokes on this syntax (asking for a semi-colon after 'inputPort'),
suggesting to me that multidimensional arrays are not being
supported. Has anyone else seen a problem like this?

Thanks,
Jake

 

[gtwrek@pacbell.net]

On Sep 11, 12:39 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

Multi-dimensional ports are simply not supported in Verilog2001. The
closest you *might* get is the use of predefined interfaces in SystemVerilog
but I would doubt that would work as well. It's been desirable in the past
to have 2-D ports but they just aren't supported in the language. Using one
large 1-D port that takes a concatenation of the individual ports is a
workaround.

Actually, multi-dimensional arrays as ports work just fine in
SystemVerilog. Arrays
are "first-class" citizens in Systemverilog, thus can be used just
about
anywhere a normal vectored wire could be.

Jake, I haven't used NCSIM in a while, but see if you can just add a "-
sv" switch
or similar to tell the tool to compile as Systemverilog, and see if
that works.

You can also use "real" types (and arrays of reals) on ports too.
This might
be more useful to you than fixed 64-bit vectors.

The last alternative, (for Verilog-2001) is as John suggests, just
blasting out
the long array into a long wire i.e:

input [ (64 * 10 ) - 1 : 0 ] InputPort.

Where you instaciate the module in the upper level use the
concatenation feature in verilog:

wire [63 : 0 ] Inputdata [ 9 : 0 ];

..InputPort( { Inputdata[ 9 ], Inputdata[ 8 ], ..., Inputdata[ 0 ] } )

Regards,

Mark

 

[John_H]

<gtwrek@pacbell.net> wrote in message
news:1189544201.735994.126500@q5g2000prf.googlegroups.com...
<snip>

Actually, multi-dimensional arrays as ports work just fine in
SystemVerilog. Arrays
are "first-class" citizens in Systemverilog, thus can be used just
about
anywhere a normal vectored wire could be.
snip

I appreciate this information. I've been waiting to start with SV since
full rollout of support for Verilog2001 took so long. I look forward to
doing more, better.