555 timer

R

RKovach

Guest
I am trying to get an astable output of 4ms on, and 20ms off from a 555
timer. Is this possible? I have no problem getting the opposite times, 20ms
on and 4ms off. When I try to reverse the resistor values, the duty cycle is
50%. If I use a simple inverter circuit with a resistor and transistor at
the output, I get the output I need. The problem with this is, when the
timer stops, the output is V+, not ground.
 
RKovach wrote:
I am trying to get an astable output of 4ms on, and 20ms off from a
555 timer. Is this possible? I have no problem getting the opposite
times, 20ms on and 4ms off. When I try to reverse the resistor
values, the duty cycle is 50%. If I use a simple inverter circuit
with a resistor and transistor at the output, I get the output I
need. The problem with this is, when the timer stops, the output is
V+, not ground.
Click to expand...
You can do this by connecting a diode: anode to pin 7, cathode to pin 6.
 
CFoley1064 wrote:
Like this (view in fixed font or M$ Notepad):

VCC VCC
+ +
| |
| o---.
.-. | |
| | .---o---o----.
R1| | | 8 4 |
'-' | |
| | |
| | |
.----o-----o7 3o------
| | | 555 |
| .-. | |
D - | | | |
^ R2| | .--o6 |
| '-' | | |
| | | | |
'----o--o--o2 |
| | 1 5 |
C | '----o---o---'
--- | |
--- | NC
| |
=== ===
GND GND
Click to expand...
The diode should be the other way around.
 
Subject: Re: 555 timer
From: "Andrew Holme" andrew@nospam.com
Date: 10/30/2004 6:22 PM Central Daylight Time
Message-id: <cm18h9$8ip$1$830fa7a5@news.demon.co.uk


VCC VCC
+ +
| |
| o---.
.-. | |
| | .---o---o----.
R1| | | 8 4 |
'-' | |
| | |
| | |
.----o-----o7 3o------
| | | 555 |
| .-. | |
D - | | | |
^ R2| | .--o6 |
| '-' | | |
| | | | |
'----o--o--o2 |
| | 1 5 |
C | '----o---o---'
--- | |
--- | NC
| |
=== ===
GND GND

The diode should be the other way around.
Click to expand...
Yep. Backwards, Sorry.

Chris
 
On Sat, 30 Oct 2004 17:33:01 -0700, "Max Hauser"
<maxREMOVE@THIStdl.com> wrote:

Argh! The Thing that Wouldn't Die. With full respect for H. Camenzind and
the others involved, and for its obvious commercial success, and for RKovach
who posed a reasonable question here, the enduring popularity of this
product (including among hobbyists) mystifies me, basis in a moment.

"RKovach" in news:10o81ro8krnap6c@corp.supernews.com...
I am trying to get an astable output of 4ms on, and 20ms
off from a 555 timer. Is this possible?

I believe it is, others have offered details already. For the record though
this may not have the frequency stability or other properties needed by the
specific application, a decent astable oscillator with near-minimum
component count can always be made be putting a resistor from output to
input of a CMOS logic inverter or inverting gate of Schmitt, or hysteresis,
type, and then a capacitor from the logic input to ground (or to a power
supply).
Click to expand...
NOT quite that simple. Stable/self-starting oscillators need 3
inverters... see CMOS*.pdf on the SED/Schematics page of my website.

Asymmetrical duty cycles are available with additional components;
one way is to split the feedback resistor into two parallel paths, each with
a resistor and a diode, one in each direction; each resistor then controls
one charging ramp at the capacitor, and can be adjusted independently.
Click to expand...
Can be done also with the 555, just don't use the built-in discharge
path.

[snip]

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
"RKovach" <rkovach@execpc.com> wrote:

I am trying to get an astable output of 4ms on, and 20ms off from a 555
timer. Is this possible? I have no problem getting the opposite times, 20ms
on and 4ms off. When I try to reverse the resistor values, the duty cycle is
50%. If I use a simple inverter circuit with a resistor and transistor at
the output, I get the output I need. The problem with this is, when the
timer stops, the output is V+, not ground.
Click to expand...
Here you go:
http://www.terrypin.dial.pipex.com/Images/AstableRKovach.gif

--
Terry Pinnell
Hobbyist, West Sussex, UK
 
On Sun, 31 Oct 2004 01:49:32 -0800, "Max Hauser"
<maxREMOVE@THIStdl.com> wrote:

"Jim Thompson" <thegreatone@example.com> in
news:tjf8o013guvl6qv6g0qp26u2jo2kegqamt@4ax.com...
On Sat, 30 Oct 2004 17:33:01 -0700, "Max Hauser" wrote:

... For the record though this may not have the frequency
stability or other properties needed by the specific application,
a decent astable oscillator with near-minimum component
count can always be made be putting a resistor from output to
input of a CMOS logic inverter or inverting gate of Schmitt,
or hysteresis, type, and then a capacitor from the logic input to
ground (or to a power supply).

NOT quite that simple. Stable/self-starting oscillators
need 3 inverters... see CMOS*.pdf on the SED/Schematics
page of my website.

With respect, Thompson: Yes, it _is_ quite that simple, at least in
context. (I have been using it for thirty years. Even you might be
surprised at what for.) Please take note of the specification of hysteretic
inverters, and the context of minimalistic alternatives to the original
SE/NE 555; frequency stability is not required. (See Paynter, 1967, for
further basis.) I think there is a theoretical possibility of a noiseless
knife-edge stable point in such oscillators but that, as the mathematicians
say, is a set of measure zero.
Click to expand...
Hysteretic Inverters aren't frequency stable over temperature and
process corners, while 3-stage-inverter types and 555/comparator types
are (or can be, if _I_ design them :)

By the way, you are overdue to come to dinner. The London Observer /
Guardian has an article just out about a place you might like to try, near
me. I could bring some wine.

http://observer.guardian.co.uk/print/0,3858,5049765-110648,00.html

[snip]

:) -- MH
Click to expand...
Indeed! If only I can make some time... business is booming to the
point that I'm scarfing up money even on weekends ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
In article <10o81ro8krnap6c@corp.supernews.com>,
RKovach <rkovach@execpc.com> wrote:
I am trying to get an astable output of 4ms on, and 20ms off from a 555
timer. Is this possible? I have no problem getting the opposite times, 20ms
on and 4ms off. When I try to reverse the resistor values, the duty cycle is
50%. If I use a simple inverter circuit with a resistor and transistor at
the output, I get the output I need. The problem with this is, when the
timer stops, the output is V+, not ground.
Click to expand...
Noone else has said it so I will have to:

"Use a PIC"

Actually this might be the sort of job that the SOT-23 pic would do well.
It has more than enough internals to get the timing almost exact.

--
--
kensmith@rahul.net forging knowledge
 
"Jim Thompson" <thegreatone@example.com> in
news:tjf8o013guvl6qv6g0qp26u2jo2kegqamt@4ax.com...
On Sat, 30 Oct 2004 17:33:01 -0700, "Max Hauser" wrote:

... For the record though this may not have the frequency
stability or other properties needed by the specific application,
a decent astable oscillator with near-minimum component
count can always be made be putting a resistor from output to
input of a CMOS logic inverter or inverting gate of Schmitt,
or hysteresis, type, and then a capacitor from the logic input to
ground (or to a power supply).

NOT quite that simple. Stable/self-starting oscillators
need 3 inverters... see CMOS*.pdf on the SED/Schematics
page of my website.
Click to expand...
With respect, Thompson: Yes, it _is_ quite that simple, at least in
context. (I have been using it for thirty years. Even you might be
surprised at what for.) Please take note of the specification of hysteretic
inverters, and the context of minimalistic alternatives to the original
SE/NE 555; frequency stability is not required. (See Paynter, 1967, for
further basis.) I think there is a theoretical possibility of a noiseless
knife-edge stable point in such oscillators but that, as the mathematicians
say, is a set of measure zero.

By the way, you are overdue to come to dinner. The London Observer /
Guardian has an article just out about a place you might like to try, near
me. I could bring some wine.

http://observer.guardian.co.uk/print/0,3858,5049765-110648,00.html

:) -- MH
 
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