50MHz clock down to 20MHz

[weizbox]

Hello,

Im trying to get my 50MHz clock down to 20MHz and am having some
problems getting what I want done. Basicly I want to run a loop on
every clock edge of my 50MHz clock, posedge and negedge. Is there a
way to do this?


The reason why I want to run on every edge is for the timing of it to
get a 20MHz clock out of it. The pulses I will be making on the 20MHz
clock output will not have a 50% duty cycle. Rather, I plan to make
the pulses 40ns high instead of the normal 50ns, and the low state
last for 60ns since this will sync up with my 50MHz clock nicley
having 20ns pulses. Im going to be triggering on the rising edge of
the 20MHz output clock so the falling edge does not matter as much is
its 10ns short.


Thanks for the help,
-Mark

 

[weizbox]

"John_H" <johnhandwork@mail.com> wrote in message news:<Oqfed.21$OL5.2577@news-west.eli.net>...

"weizbox" <mwiesbock@gmail.com> wrote in message
news:335c6753.0410221116.76714a70@posting.google.com...
Hello,

Im trying to get my 50MHz clock down to 20MHz and am having some
problems getting what I want done. Basicly I want to run a loop on
every clock edge of my 50MHz clock, posedge and negedge. Is there a
way to do this?


The reason why I want to run on every edge is for the timing of it to
get a 20MHz clock out of it. The pulses I will be making on the 20MHz
clock output will not have a 50% duty cycle. Rather, I plan to make
the pulses 40ns high instead of the normal 50ns, and the low state
last for 60ns since this will sync up with my 50MHz clock nicley
having 20ns pulses. Im going to be triggering on the rising edge of
the 20MHz output clock so the falling edge does not matter as much is
its 10ns short.

Perhaps it would be better to enable every 2 or 3 clocks (50% mix) then have
the interface that runs at 20 MHz rearrange the data appropriately. You end
up with a single clock design with multi-cycle paths that only need to
achieve 25 MHz and you maintain the 20 MHz interfaces you appear to so
keenly desire.

If you want to run on "both edges" you'd need to either double up to 100 MHz
and use one edge direction or use a device that supports dual-edge
operation. Not too many out there.

John,

Thanks for the pointer. Over the weekend I managed to get something
that ended up working out quite well. I couldnt use the method of
enabling every 2 or 3 clocks because it had to really be exactly on
20MHz. As well I didnt have a 100MHz clock to use, only the 50MHz.

What I came up with instead was using three loops, one triggering on a
50MHz positive edge, one on a 50MHz negative and one just set as
'always'. Setting it up this way allows me to get a loop iteration
every 20ns. Since the period of a 20MHz clock is 100ns, we should be
able to work this out with our 20ns resolution, all we need to do is
count the number of edges (positive and negative) and set up an always
case statement to set up our 20MHz pulses at the appropriate times
during the count.

Using this method, the duty cycle is NOT 50%, but generaly this does
not matter is much since most of the time only one edge is used for
timing, like in this case where I needed a 20MHz clock for a 10BASE
ethernet application.

Heres the code:

module clock(clk50, clk20);

input clk50; // 50MHz clock

reg clk20; //20MHz clock

reg [7:0]pcount; // Number of Positive edges
reg [7:0]ncount; // Number of Negative edges
reg [7:0]tcount; // Total Count of edges

always
tcount = (ncount + pcount);

always
begin
case (tcount)
0: clk20 = 1; // Only for first run, set to high
2: clk20 = 0; // 40ns has gone by, set to low
5: clk20 = 1; // 100ns has gone by, period complete, set to high
7: clk20 = 0; //140ns has gone by, set to low
10: clk20 = 1; //200ns has gone by, 2 periods complete, reset cycle,
set high
default: ;
endcase
end

always @(posedge clk50)
begin
pcount = pcount + 1;
case (pcount)
5: pcount = 0;
default: ;
endcase
end

always @(negedge clk50)
begin
ncount = ncount + 1;
case (ncount)
6: ncount = 1; //Set to 1 on first falling edge after 2 periods
complete
default: ;
endcase
end


I know this may not be the best method to do something like this since
I am fairly new to Verilog and FPGAs, but it does work when only
needing one edge (pos or neg) for timeing. From using this method you
can create any frequency below below the current clock rate you have
as long as the period is evenly dividable by you clocks pulse width.


-Mark