50MHz A/D total unadjusted error of 4LSBs Max

D

Denis Gleeson

Guest
Hello all

I am paralleling two A/Ds to double the conversion rate on one.
ideally I want to get an A/D which will sample at 50MHz and
have very low maximum error.

ie. something like.

Gain (or Full scale) error max : 2 LSB
Offset error max : 2 LSB
INL max : 1 LSB
DNL max : 1 LSB

While I know I could adjust out Gain and Offset error this would require
4 adjustable reference ccts and a lot of tweaking.

Anybody suggest a part?

many thanks for any help.

Denis
 
You didn't mention how many bits you want. If it's 14 or less, why
not just use a single fast ADC? I think you are grossly
underestimating the problems involved in getting two ADCs to properly
digitize a wide bandwidth signal...DC specs do not even begin to tell
the story.

Cheers,
Tom

dgleeson-2@utvinternet.com (Denis Gleeson) wrote in message news:<184c35f9.0308190217.7d84d2c7@posting.google.com>...
Hello all

I am paralleling two A/Ds to double the conversion rate on one.
ideally I want to get an A/D which will sample at 50MHz and
have very low maximum error.

ie. something like.

Gain (or Full scale) error max : 2 LSB
Offset error max : 2 LSB
INL max : 1 LSB
DNL max : 1 LSB

While I know I could adjust out Gain and Offset error this would require
4 adjustable reference ccts and a lot of tweaking.

Anybody suggest a part?

many thanks for any help.

Denis
Click to expand...
 
"Tom Bruhns" <k7itm@aol.com> wrote in message
news:3200347.0308191043.101fe84b@posting.google.com...
You didn't mention how many bits you want. If it's 14 or less, why
not just use a single fast ADC? I think you are grossly
underestimating the problems involved in getting two ADCs to properly
digitize a wide bandwidth signal...DC specs do not even begin to tell
the story.
Click to expand...
Yes, I agree - matching the phase on the clock to the 2 ADCs will be the
most difficult. I think phase mismatch shows up as phase noise (or a spur).
AD6644 is one part that comes to mind immediately - 14 bits @ 65MHz. There
is a Linear Tech part that has slightly better specs in this same range.

Cheers
Bhaskar

Cheers,
Tom

dgleeson-2@utvinternet.com (Denis Gleeson) wrote in message
news:<184c35f9.0308190217.7d84d2c7@posting.google.com>...
Hello all

I am paralleling two A/Ds to double the conversion rate on one.
ideally I want to get an A/D which will sample at 50MHz and
have very low maximum error.

ie. something like.

Gain (or Full scale) error max : 2 LSB
Offset error max : 2 LSB
INL max : 1 LSB
DNL max : 1 LSB

While I know I could adjust out Gain and Offset error this would require
4 adjustable reference ccts and a lot of tweaking.

Anybody suggest a part?

many thanks for any help.

Denis
Click to expand...
 
Not knowing your application I can't be sure, but given the sampling
rate it seems that you may be using this converter in a communications
system application. I have found that for a good converter, gain
accuracy is directly traceable to the reference stability. If you are
lucky your wave form does not contain any (or much) information at DC
and you can relax the requirements accordingly and 'toss' the DC bin in
the DSP that might be following your ADC. If you can't toss the DC bin
then how about periodically self calibrating the ADC using the DSP? It
shouldn't take much horsepower to simply add or subtract a small offset
error once it is measured.

As for INL and DNL, I have found these parameters to be almost useless
when trying to determine the high speed performance of an ADC. I much
prefer ENOB, or better yet NPR (noise power ratio) if you are dealing
with multiple signals in band at the same time. You should be able to
get ENOB data from a reputable high speed converter manufacturer, and if
not it can be inferred from SINAD measurements given some decent lab
equipment and a computer.

Also, consider if you can utilize dithering to suppress conversion spurs
by placing a band limited noise signal outside the band of the signal of
interest, but within the Nyquist range of the converter. You can filter
this out downstream in a DSP easily. This method can maximize the SFDR
performance of the converter, and often allows the designer to reduce
the number of physical bits required to meet dynamic performance
requirements -- yielding a dramatic reduction in power consumption of
both the ADC and the DSP. If the converter is a sub-ranging design, you
will probably want to inject enough dithering signal to cover all of the
subranging points.

I also concur strongly that attempting to properly phase two converters
into a perfect 'ping pong' timing alignment is a highly risky approach.
Even if you get it working in the lab on a single unit at one
temperature, I believe that it will be difficult to maintain this
alignment across the temperature range and across device lot variations.
Using a single faster converter or a pair of converters on a single die
with the ping pong clocking system pre-designed would be more my style
given a choice.

Steve


Denis Gleeson wrote:
Hello all

I am paralleling two A/Ds to double the conversion rate on one.
ideally I want to get an A/D which will sample at 50MHz and
have very low maximum error.

ie. something like.

Gain (or Full scale) error max : 2 LSB
Offset error max : 2 LSB
INL max : 1 LSB
DNL max : 1 LSB

While I know I could adjust out Gain and Offset error this would require
4 adjustable reference ccts and a lot of tweaking.

Anybody suggest a part?

many thanks for any help.

Denis
Click to expand...
 
I think the phase mis-match does manifest itself as a spur in much the
same way that imperfect alignment of the phase relationships in a
quadrature modulator does. Deep down the math is similar methinks.
Probably a six-pack exercise for me (at least) to show why.

Steve


Bhaskar Thiagarajan wrote:
"Tom Bruhns" <k7itm@aol.com> wrote in message
news:3200347.0308191043.101fe84b@posting.google.com...

You didn't mention how many bits you want. If it's 14 or less, why
not just use a single fast ADC? I think you are grossly
underestimating the problems involved in getting two ADCs to properly
digitize a wide bandwidth signal...DC specs do not even begin to tell
the story.


Yes, I agree - matching the phase on the clock to the 2 ADCs will be the
most difficult. I think phase mismatch shows up as phase noise (or a spur).
AD6644 is one part that comes to mind immediately - 14 bits @ 65MHz. There
is a Linear Tech part that has slightly better specs in this same range.

Cheers
Bhaskar


Cheers,
Tom

dgleeson-2@utvinternet.com (Denis Gleeson) wrote in message

news:<184c35f9.0308190217.7d84d2c7@posting.google.com>...

Hello all

I am paralleling two A/Ds to double the conversion rate on one.
ideally I want to get an A/D which will sample at 50MHz and
have very low maximum error.

ie. something like.

Gain (or Full scale) error max : 2 LSB
Offset error max : 2 LSB
INL max : 1 LSB
DNL max : 1 LSB

While I know I could adjust out Gain and Offset error this would require
4 adjustable reference ccts and a lot of tweaking.

Anybody suggest a part?

many thanks for any help.

Denis
Click to expand...
 
Hi Steve

Using a single faster converter or a pair of converters on a single die
with the ping pong clocking system pre-designed would be more my style
given a choice.
Click to expand...
Any suggestions for high speed A/D devices with the ping pong clocking
system pre-designed?

Denis

steve <slubman@adelphia.net> wrote in message news:<3F480826.50606@adelphia.net>...
Not knowing your application I can't be sure, but given the sampling
rate it seems that you may be using this converter in a communications
system application. I have found that for a good converter, gain
accuracy is directly traceable to the reference stability. If you are
lucky your wave form does not contain any (or much) information at DC
and you can relax the requirements accordingly and 'toss' the DC bin in
the DSP that might be following your ADC. If you can't toss the DC bin
then how about periodically self calibrating the ADC using the DSP? It
shouldn't take much horsepower to simply add or subtract a small offset
error once it is measured.

As for INL and DNL, I have found these parameters to be almost useless
when trying to determine the high speed performance of an ADC. I much
prefer ENOB, or better yet NPR (noise power ratio) if you are dealing
with multiple signals in band at the same time. You should be able to
get ENOB data from a reputable high speed converter manufacturer, and if
not it can be inferred from SINAD measurements given some decent lab
equipment and a computer.

Also, consider if you can utilize dithering to suppress conversion spurs
by placing a band limited noise signal outside the band of the signal of
interest, but within the Nyquist range of the converter. You can filter
this out downstream in a DSP easily. This method can maximize the SFDR
performance of the converter, and often allows the designer to reduce
the number of physical bits required to meet dynamic performance
requirements -- yielding a dramatic reduction in power consumption of
both the ADC and the DSP. If the converter is a sub-ranging design, you
will probably want to inject enough dithering signal to cover all of the
subranging points.

I also concur strongly that attempting to properly phase two converters
into a perfect 'ping pong' timing alignment is a highly risky approach.
Even if you get it working in the lab on a single unit at one
temperature, I believe that it will be difficult to maintain this
alignment across the temperature range and across device lot variations.
Using a single faster converter or a pair of converters on a single die
with the ping pong clocking system pre-designed would be more my style
given a choice.

Steve


Denis Gleeson wrote:
Hello all

I am paralleling two A/Ds to double the conversion rate on one.
ideally I want to get an A/D which will sample at 50MHz and
have very low maximum error.

ie. something like.

Gain (or Full scale) error max : 2 LSB
Offset error max : 2 LSB
INL max : 1 LSB
DNL max : 1 LSB

While I know I could adjust out Gain and Offset error this would require
4 adjustable reference ccts and a lot of tweaking.

Anybody suggest a part?

many thanks for any help.

Denis
Click to expand...
 
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