M
Matt Cohen
Guest
I'm working on a design with a Xilinx XC95XL series CPLD. The inputs
would be coming from a system with a 5 V (possibly higher, I don't
have the exact number yet) output. I need 3.3 V outputs, so using the
separate I/O power supply is not a good solution. As a novice
engineer, I have a few ideas, but don't know which is best. Is there
a problem with using a simple resistor divider to create lower
voltages? Should I have to use a separate level shifter IC instead to
change the 5 V signals to 3.3 V? Thanks,
Matt Cohen
would be coming from a system with a 5 V (possibly higher, I don't
have the exact number yet) output. I need 3.3 V outputs, so using the
separate I/O power supply is not a good solution. As a novice
engineer, I have a few ideas, but don't know which is best. Is there
a problem with using a simple resistor divider to create lower
voltages? Should I have to use a separate level shifter IC instead to
change the 5 V signals to 3.3 V? Thanks,
Matt Cohen