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Taufik Siswanto
Guest
I wonder why FPGA Express can't directly infer 5 input LUT, a feature of virtex (even xc5200), even for obvious expression such as: <p>y <= a and b and c and d and e; <p>Would anyone tell the workaround, if any, to this problem. Thank you. <p>Regards, <BR>
Taufik Siswanto
Taufik Siswanto