L
Lostgallifreyan
Guest
I Googled to chance my luck finding a model, after not finding one from NXP.
My observations found a few points:
1. Lots of people asking, not finding.
2. One poster saying that PLL's were hard to make because of something to do
with two time slices or something that I didn't understand at all.
3. Jim Thompson saying he'd made one.
It may be that I shouldn't be spicing this if it is hard to do, because if
the HEF4046B's VCO frequency isn't very linear in proportion with input
voltage, I'd need to do something beyond the device itself anyway. I
understand that the linearity only matters for stability because the output
frequency and phase is what matters, but in my case I'll want to use an LM331
as oscilator followed by a flip-flop to get a square wave, or some other
means of coercing high linearity out of the PLL voltage output normally fed
to pin 9.
If there IS a good spice model of the CMOS HEF4046B, please can someone point
me at it, because it will be very useful to me, and it may be that the device
is linear enough as it is. I've already put a working pitch tracker together
ona pin deck, but a good spice model would be great to help complete a model
to help understand what's going on in there.
PS. (Maybe better posted to SED but neater kept here, I think)...
If I want to reduce ripple, and create a faster response to an output
frequency for any downstream circuit I might try, it seems that divisions in
the feedback loop are a neat way to go. Question is: would this cause the
lock to a sudden arrival of a new audio frequency to be slower than if I had
no divisions in the loop to multiply it for output? Specifically, if it slows
more than the response to an un-multiplied frequency would be slowed by a
very linear frequency-to-voltage IC like LM331, then multiplying it to speed
the LM331 response could be pointless, as circuit complexity rises for no
useful result. Clearly this is a good task for Spice to test quickly, IF
there was a good 4046 PLL model to do it with.
My observations found a few points:
1. Lots of people asking, not finding.
2. One poster saying that PLL's were hard to make because of something to do
with two time slices or something that I didn't understand at all.
3. Jim Thompson saying he'd made one.
It may be that I shouldn't be spicing this if it is hard to do, because if
the HEF4046B's VCO frequency isn't very linear in proportion with input
voltage, I'd need to do something beyond the device itself anyway. I
understand that the linearity only matters for stability because the output
frequency and phase is what matters, but in my case I'll want to use an LM331
as oscilator followed by a flip-flop to get a square wave, or some other
means of coercing high linearity out of the PLL voltage output normally fed
to pin 9.
If there IS a good spice model of the CMOS HEF4046B, please can someone point
me at it, because it will be very useful to me, and it may be that the device
is linear enough as it is. I've already put a working pitch tracker together
ona pin deck, but a good spice model would be great to help complete a model
to help understand what's going on in there.
PS. (Maybe better posted to SED but neater kept here, I think)...
If I want to reduce ripple, and create a faster response to an output
frequency for any downstream circuit I might try, it seems that divisions in
the feedback loop are a neat way to go. Question is: would this cause the
lock to a sudden arrival of a new audio frequency to be slower than if I had
no divisions in the loop to multiply it for output? Specifically, if it slows
more than the response to an un-multiplied frequency would be slowed by a
very linear frequency-to-voltage IC like LM331, then multiplying it to speed
the LM331 response could be pointless, as circuit complexity rises for no
useful result. Clearly this is a good task for Spice to test quickly, IF
there was a good 4046 PLL model to do it with.