4013 question

eatmorepies · Apr 4, 2012

I want the D type latch (using CMOS 4013) to remember a momentary signal and
output high. When the momentary signal arrives a second time I want the
output to drop low.

The input signal (from sensor circuit) goes high when the light sensor is
shadowed (checked with logic probe), this is connected to the clock - pin 3.

Q (pin 1) connected to a 1k resistor in series with an LED to zero volts.

Not Q (pin 2) connected to data - pin 5.

Set (pin 6) and reset (pin 4) connected to pin 7 - Vss.

Pin 14 is Vcc at 10V.

As I shadow or illuminate the sensor the output of the sensor circuit goes
high or low as required. I'm using an op-amp as a comparator.

Q remains high all the time - irrespective of the clock signal going low,
high, low. The LED is always on. Not Q remains low at all times.

Looking at Q with the logic probe as the clock goes high there is a
monentary pulse but the output still stays high. Looking at not Q there is a
momentary pulse when the clock goes high but the output still stays low.

The signals are the same when I remove the load (the LED) from the 4013.

Why don't Q and not Q swap levels when the clock goes high?

John

petrus bitbyter · Apr 4, 2012

"eatmorepies" <jckipper@lineone.net> schreef in bericht
news:9u3335Fp7pU1@mid.individual.net...

I want the D type latch (using CMOS 4013) to remember a momentary signal
and output high. When the momentary signal arrives a second time I want the
output to drop low.

The input signal (from sensor circuit) goes high when the light sensor is
shadowed (checked with logic probe), this is connected to the clock - pin
3.

Q (pin 1) connected to a 1k resistor in series with an LED to zero volts.

Not Q (pin 2) connected to data - pin 5.

Set (pin 6) and reset (pin 4) connected to pin 7 - Vss.

Pin 14 is Vcc at 10V.

As I shadow or illuminate the sensor the output of the sensor circuit goes
high or low as required. I'm using an op-amp as a comparator.

Q remains high all the time - irrespective of the clock signal going low,
high, low. The LED is always on. Not Q remains low at all times.

Looking at Q with the logic probe as the clock goes high there is a
monentary pulse but the output still stays high. Looking at not Q there is
a momentary pulse when the clock goes high but the output still stays low.

The signals are the same when I remove the load (the LED) from the 4013.

Why don't Q and not Q swap levels when the clock goes high?

John

What did you connect to the D input? It should be connected to not Q to get
the required memory function.

petrus bitbyter

John Fields · Apr 4, 2012

On Wed, 4 Apr 2012 15:10:53 +0100, "eatmorepies"
<jckipper@lineone.net> wrote:

I want the D type latch (using CMOS 4013) to remember a momentary signal and
output high. When the momentary signal arrives a second time I want the
output to drop low.

The input signal (from sensor circuit) goes high when the light sensor is
shadowed (checked with logic probe), this is connected to the clock - pin 3.

Q (pin 1) connected to a 1k resistor in series with an LED to zero volts.

Not Q (pin 2) connected to data - pin 5.

Set (pin 6) and reset (pin 4) connected to pin 7 - Vss.

Pin 14 is Vcc at 10V.

As I shadow or illuminate the sensor the output of the sensor circuit goes
high or low as required. I'm using an op-amp as a comparator.

Q remains high all the time - irrespective of the clock signal going low,
high, low. The LED is always on. Not Q remains low at all times.

Looking at Q with the logic probe as the clock goes high there is a
monentary pulse but the output still stays high. Looking at not Q there is a
momentary pulse when the clock goes high but the output still stays low.

The signals are the same when I remove the load (the LED) from the 4013.

Why don't Q and not Q swap levels when the clock goes high?

John

---
Do you have pin 7 connected to the power supply 0V and all of the
inputs on the second dflop connected to either Vee or Vdd?

--
JF

Tim Wescott · Apr 4, 2012

On Wed, 04 Apr 2012 15:10:53 +0100, eatmorepies wrote:

I want the D type latch (using CMOS 4013) to remember a momentary signal
and output high. When the momentary signal arrives a second time I want
the output to drop low.

The input signal (from sensor circuit) goes high when the light sensor
is shadowed (checked with logic probe), this is connected to the clock -
pin 3.

Q (pin 1) connected to a 1k resistor in series with an LED to zero
volts.

Not Q (pin 2) connected to data - pin 5.

Set (pin 6) and reset (pin 4) connected to pin 7 - Vss.

Pin 14 is Vcc at 10V.

As I shadow or illuminate the sensor the output of the sensor circuit
goes high or low as required. I'm using an op-amp as a comparator.

Q remains high all the time - irrespective of the clock signal going
low, high, low. The LED is always on. Not Q remains low at all times.

Looking at Q with the logic probe as the clock goes high there is a
monentary pulse but the output still stays high. Looking at not Q there
is a momentary pulse when the clock goes high but the output still stays
low.

The signals are the same when I remove the load (the LED) from the 4013.

Why don't Q and not Q swap levels when the clock goes high?

Do you have a clean, fast (enough), debounced clock signal?

Is the power supply to the chip bypassed?

It sounds like you're double-clocking the chip, for one reason or
another. Why it happens to prefer one state over another -- I dunno.
But cleanly capturing events like this can be a bitch and a half.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

Jim Thompson · Apr 4, 2012

On Wed, 04 Apr 2012 12:24:22 -0500, John Fields
<jfields@austininstruments.com> wrote:

On Wed, 4 Apr 2012 15:10:53 +0100, "eatmorepies"
jckipper@lineone.net> wrote:

I want the D type latch (using CMOS 4013) to remember a momentary signal and
output high. When the momentary signal arrives a second time I want the
output to drop low.

The input signal (from sensor circuit) goes high when the light sensor is
shadowed (checked with logic probe), this is connected to the clock - pin 3.

Q (pin 1) connected to a 1k resistor in series with an LED to zero volts.

Not Q (pin 2) connected to data - pin 5.

Set (pin 6) and reset (pin 4) connected to pin 7 - Vss.

Pin 14 is Vcc at 10V.

As I shadow or illuminate the sensor the output of the sensor circuit goes
high or low as required. I'm using an op-amp as a comparator.

Q remains high all the time - irrespective of the clock signal going low,
high, low. The LED is always on. Not Q remains low at all times.

Looking at Q with the logic probe as the clock goes high there is a
monentary pulse but the output still stays high. Looking at not Q there is a
momentary pulse when the clock goes high but the output still stays low.

The signals are the same when I remove the load (the LED) from the 4013.

Why don't Q and not Q swap levels when the clock goes high?

John

---
Do you have pin 7 connected to the power supply 0V and all of the
inputs on the second dflop connected to either Vee or Vdd?

eatmorepies · Apr 4, 2012

"John Fields" <jfields@austininstruments.com> wrote in message
news:bm0pn7tphul0cj7squis78hp2vvia7lp3t@4ax.com...

On Wed, 4 Apr 2012 15:10:53 +0100, "eatmorepies"
jckipper@lineone.net> wrote:

I want the D type latch (using CMOS 4013) to remember a momentary signal
and
output high. When the momentary signal arrives a second time I want the
output to drop low.

The input signal (from sensor circuit) goes high when the light sensor is
shadowed (checked with logic probe), this is connected to the clock - pin
3.

Q (pin 1) connected to a 1k resistor in series with an LED to zero volts.

Not Q (pin 2) connected to data - pin 5.

Set (pin 6) and reset (pin 4) connected to pin 7 - Vss.

Pin 14 is Vcc at 10V.

As I shadow or illuminate the sensor the output of the sensor circuit goes
high or low as required. I'm using an op-amp as a comparator.

Q remains high all the time - irrespective of the clock signal going low,
high, low. The LED is always on. Not Q remains low at all times.

Looking at Q with the logic probe as the clock goes high there is a
monentary pulse but the output still stays high. Looking at not Q there is
a
momentary pulse when the clock goes high but the output still stays low.

The signals are the same when I remove the load (the LED) from the 4013.

Why don't Q and not Q swap levels when the clock goes high?

John

---
Do you have pin 7 connected to the power supply 0V and all of the
inputs on the second dflop connected to either Vee or Vdd?

Sorry - forgot to mention I had connected pin7 to 0V.

I've just tried again with the inputs of the second Dtype grounded - R, S,
Clk and D. No change in the circuit's behaviour.

John

eatmorepies · Apr 4, 2012

Do you have a clean, fast (enough), debounced clock signal?

I don't know because I don't have a scope. I'm guessing the pulse flash on
the logic probe tells me the clock signal isn't clean.

Is the power supply to the chip bypassed?

I'm not sure what this means. I have a 0.1 microF ceramic decoupling
capactior across the power supply.

It sounds like you're double-clocking the chip, for one reason or
another.

I think you're right.

Would a Schmitt nand (4093) configured an an inverter be sufficient to
de-bounce the signal? if not what do you suggest?

John

eatmorepies · Apr 4, 2012

"eatmorepies" <jckipper@lineone.net> wrote in message
news:9u3n4sFmj2U1@mid.individual.net...

Do you have a clean, fast (enough), debounced clock signal?

I don't know because I don't have a scope. I'm guessing the pulse flash on
the logic probe tells me the clock signal isn't clean.

Is the power supply to the chip bypassed?

I'm not sure what this means. I have a 0.1 microF ceramic decoupling
capactior across the power supply.

It sounds like you're double-clocking the chip, for one reason or
another.

I think you're right.

Would a Schmitt nand (4093) configured an an inverter be sufficient to
de-bounce the signal? if not what do you suggest?

I've just tried the 4093 Schmitt NAND (I put 2 inseries to make a Schmitt
AND), The circuit is much improved and it switches states cleanly about 8 of
10 times.

Now. How to make the initial pulse last longer using some kind of monostable
with a delay before it falls back to it's stable state?

John

Tim Wescott · Apr 4, 2012

On Wed, 04 Apr 2012 21:03:21 +0100, eatmorepies wrote:

"eatmorepies" <jckipper@lineone.net> wrote in message
news:9u3n4sFmj2U1@mid.individual.net...

Do you have a clean, fast (enough), debounced clock signal?

I don't know because I don't have a scope. I'm guessing the pulse flash
on the logic probe tells me the clock signal isn't clean.

Is the power supply to the chip bypassed?

I'm not sure what this means. I have a 0.1 microF ceramic decoupling
capactior across the power supply.

It sounds like you're double-clocking the chip, for one reason or
another.

I think you're right.

Would a Schmitt nand (4093) configured an an inverter be sufficient to
de-bounce the signal? if not what do you suggest?

I've just tried the 4093 Schmitt NAND (I put 2 inseries to make a
Schmitt AND), The circuit is much improved and it switches states
cleanly about 8 of 10 times.

Now. How to make the initial pulse last longer using some kind of
monostable with a delay before it falls back to it's stable state?

John

It sounds like you've found the answer with your 555 circuit, but if you
Google "debounce circuit" you'll find a bunch of suggestions.

Note that debouncing is as much an art as a science, so expect that you
may have to make a couple of passes to get it right.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

Jasen Betts · Apr 5, 2012

On 2012-04-04, eatmorepies <jckipper@lineone.net> wrote:

I've just tried the 4093 Schmitt NAND (I put 2 inseries to make a Schmitt
AND), The circuit is much improved and it switches states cleanly about 8 of
10 times.

Now. How to make the initial pulse last longer using some kind of monostable
with a delay before it falls back to it's stable state?

an easy way to do that with what you have is to put a R-C low-pass
filter between the two schmitt NAND stages.

______ ______
.--| __ \ .--| __ \
---+ | _// )O---[100K]---+------+ | _// )o---
`--|______/ | `--|______/
===
| 100nF
0V--+--

--
ââ 100% natural

John Fields · Apr 5, 2012

On Wed, 04 Apr 2012 11:16:45 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Wed, 04 Apr 2012 12:24:22 -0500, John Fields
jfields@austininstruments.com> wrote:

On Wed, 4 Apr 2012 15:10:53 +0100, "eatmorepies"
jckipper@lineone.net> wrote:

I want the D type latch (using CMOS 4013) to remember a momentary signal and
output high. When the momentary signal arrives a second time I want the
output to drop low.

The input signal (from sensor circuit) goes high when the light sensor is
shadowed (checked with logic probe), this is connected to the clock - pin 3.

Q (pin 1) connected to a 1k resistor in series with an LED to zero volts.

Not Q (pin 2) connected to data - pin 5.

Set (pin 6) and reset (pin 4) connected to pin 7 - Vss.

Pin 14 is Vcc at 10V.

As I shadow or illuminate the sensor the output of the sensor circuit goes
high or low as required. I'm using an op-amp as a comparator.

Q remains high all the time - irrespective of the clock signal going low,
high, low. The LED is always on. Not Q remains low at all times.

Looking at Q with the logic probe as the clock goes high there is a
monentary pulse but the output still stays high. Looking at not Q there is a
momentary pulse when the clock goes high but the output still stays low.

The signals are the same when I remove the load (the LED) from the 4013.

Why don't Q and not Q swap levels when the clock goes high?

John

---
Do you have pin 7 connected to the power supply 0V and all of the
inputs on the second dflop connected to either Vee or Vdd?

How about the clock edge-rate?

...Jim Thompson

--- _
Probably not much of a concern since he's seeing action on Q and Q.
_
Since Q and Q always wind up in the same place after the clock is
asserted, I'd suspect double-pulsing on the clock input.

Relatively slowly, too, since his double Schmitt trigger only cured
the problem 80% of the time and that handy-dandy 555 with a 2 second
delay did the trick.

--
JF

4013 question

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