4-layer - which layer for ground, power?

[Richard H.]

In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer
signal layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the SMT
component side; or

c) a hybrid with ground layer on top, power on layer 2 (for
capacitance), and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer without
cutting up the power planes with traces. OTOH, 'b' and 'c' would
support small "escape" traces on the top layer without cutting up the
ground plane too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?

Thanks,
Richard

 

[Guy Macon]

Richard H. wrote:

In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer
signal layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the SMT
component side; or

c) a hybrid with ground layer on top, power on layer 2 (for
capacitance), and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer without
cutting up the power planes with traces. OTOH, 'b' and 'c' would
support small "escape" traces on the top layer without cutting up the
ground plane too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?

Keep in mind that some board houses make the thickness between
2 and 3 smaller by default. More capaciance is good for PWR/GND,
not so good for signals.

Cutting up the power/ground plane with traces isn't always bad.
a few very short traces to jump over problems can make a huge
difference in the routability of the project.

 

[Guy Macon]

PeteS wrote:

The inner layers on a 4 layer board are on core material.

Like this:

Outer layer ---------------- Cu
Prepreg --------------------
Inner layer ---------------- Cu
Core (FR4 or whatever)
Inner layer ---------------- Cu
Prepreg --------------------
Outer layer ---------------- Cu

Or sometimes like this:

Outer layer ----------------- Cu

Core (FR4 or whatever)
Inner layer ----------------- Cu

Prepreg ---------------------
Inner layer ----------------- Cu

Core (FR4 or whatever)
Outer layer ----------------- Cu

Not so common on US-made boards, but you see it on some really
low-cost/high-volume asian boards. Sometimes the only vias
through that middle layer are component leads and the board
is double-thick - because they are really a 2-layer board
house that glues two 2-layer boards together to make a 4-layer
board.

 

[Fred Bartoli]

"Tim Shoppa" <shoppa@trailing-edge.com> a écrit dans le message de
news:1118779047.453269.228240@z14g2000cwz.googlegroups.com...

Superstitions?

Well, I usually mount my components on the outside layers of the PC
board, so that's where my signal tracks go.

You're free to mount them in the inside layers of the PCB if you want
.

Or if you insist on mounting the components outside you'll have to have one
via per pad. You don't have those when your signal tracks are one the outer
layers.

Plus components pads + signal pads exit vias + routing vias = lots of holes
in your outside ground/power planes, i.e. probably more EMC problem than
solved.


--
Thanks,
Fred.

 

[Richard H.]

mike wrote:

You need symmetry relative to the center of the board stack.
If you put the planes toward one side, the board can warp significantly.

Ah, yes. I'd read about this, and promptly forgot about it.

I've seen comments about hatching the fill instead of using a solid
plane, also for warping reasons - is this a valid concern?

 

[Richard H.]

Fred Bartoli wrote:

Or if you insist on mounting the components outside you'll have to have one
via per pad. You don't have those when your signal tracks are one the outer
layers.

Plus components pads + signal pads exit vias + routing vias = lots of holes
in your outside ground/power planes, i.e. probably more EMC problem than
solved.

Point taken. This design is 4-6 devices on a ~40-line bus, so there's
no hope of keeping the traces on one layer anyway, but keeping to 2
layers for signals means one set of vias for each device, instead of
two. Two layers is fairly compact, but the power and ground fills are
pretty chopped up, so that's why the 4-layer interest.

 

[Richard H.]

PeteS wrote:

Generally speaking, your full plane layers should be internal. Keep in
mind you can always 'bore through' for a signal that really needs to be
internal.

Good points, thanks. It seems some more creative layout is in order to
compress the 2-layer signal layout, then add the center power planes,
rather than double the vias and spreading the signals across 3 layers.

So, who are good shops for 4-layer protos? (We're in the US.)

From dredging the back of trade mags, it seems Sierra Proto Express has
the competition beat on pricing - for a 4x6" board, they're about $125
for batch of 2 boards. Everyone else ranges $200 - $400 per batch
minimum. Is there a catch?

 

[Tam/WB2TT]

"Richard H." <rh86@no.spam> wrote in message
news:3sFre.8174$Ta7.4666@fed1read04...

In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer signal
layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the SMT
component side; or

c) a hybrid with ground layer on top, power on layer 2 (for capacitance),
and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer without
cutting up the power planes with traces. OTOH, 'b' and 'c' would support
small "escape" traces on the top layer without cutting up the ground plane
too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?

Thanks,
Richard

Richard,
Mostly as an experiment, I once did a modified version of your "B". We
already has some boards of the conventional type with the signal layers
being 1 & 4. So, without changing the placement, we made up some boards with
the signal layers as 2 & 3. Ground was 1 and VCC was 4. What helped was that
we snuck some short signal traces on layers 1 & 4. Audits showd that all
crosstalk numbers dropped by a factor of two by having buried signal layers;
possibly due to slower rise times. Anyhow, we went to production with
Plan-B, and there were never any problems. This was a memory board with
through hole DRAMs. Not sure I would want to do it with SM.

Tam

 

[mike]

Richard H. wrote:

mike wrote:

You need symmetry relative to the center of the board stack.
If you put the planes toward one side, the board can warp significantly.


Ah, yes. I'd read about this, and promptly forgot about it.

I've seen comments about hatching the fill instead of using a solid
plane, also for warping reasons - is this a valid concern?

That's a question for your vendor.
Problem is that they ship you a flat board. You run it through reflow
and it warps. Still not much problem until you install it into a
package designed for a flat board that straightens it out. And your
SMT parts start cracking...just after you shipped it...
mike

--
Return address is VALID but some sites block emails
with links. Delete this sig when replying.
..
Wanted, PCMCIA SCSI Card for HP m820 CDRW.
FS 500MHz Tek DSOscilloscope TDS540 Make Offer
Wanted 12" LCD for Compaq Armada 7770MT.
Bunch of stuff For Sale and Wanted at the link below.
MAKE THE OBVIOUS CHANGES TO THE LINK
ht<removethis>tp://www.geocities.com/SiliconValley/Monitor/4710/

 

[mike]

Tam/WB2TT wrote:

"Richard H." <rh86@no.spam> wrote in message
news:3sFre.8174$Ta7.4666@fed1read04...

In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer signal
layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the SMT
component side; or

c) a hybrid with ground layer on top, power on layer 2 (for capacitance),
and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer without
cutting up the power planes with traces. OTOH, 'b' and 'c' would support
small "escape" traces on the top layer without cutting up the ground plane
too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?

Thanks,
Richard


Richard,
Mostly as an experiment, I once did a modified version of your "B". We
already has some boards of the conventional type with the signal layers
being 1 & 4. So, without changing the placement, we made up some boards with
the signal layers as 2 & 3. Ground was 1 and VCC was 4. What helped was that
we snuck some short signal traces on layers 1 & 4. Audits showd that all
crosstalk numbers dropped by a factor of two by having buried signal layers;
possibly due to slower rise times. Anyhow, we went to production with
Plan-B, and there were never any problems. This was a memory board with
through hole DRAMs. Not sure I would want to do it with SM.

Tam

Assume you have a pair of bus traces above a ground plane.
All is good...
Now, cut a slot in the ground plane under the traces as you would to try
to put traces on that plane too.
You've just installed a coupled inductor in series with your bus traces.
All is bad.
You'll find pattern dependent errors that will drive you nutz if you're
lucky enough to find the symptom before your customer sends it back
'cause it don't work.
You can usually "get away" with some of this stuff...it's all a tradeoff.
mike


--
Return address is VALID but some sites block emails
with links. Delete this sig when replying.
..
Wanted, PCMCIA SCSI Card for HP m820 CDRW.
FS 500MHz Tek DSOscilloscope TDS540 Make Offer
Wanted 12" LCD for Compaq Armada 7770MT.
Bunch of stuff For Sale and Wanted at the link below.
MAKE THE OBVIOUS CHANGES TO THE LINK
ht<removethis>tp://www.geocities.com/SiliconValley/Monitor/4710/

 

[Tam/WB2TT]

"mike" <spamme0@netscape.net> wrote in message
news:42AF7EBA.7030803@netscape.net...

Assume you have a pair of bus traces above a ground plane.
All is good...
Now, cut a slot in the ground plane under the traces as you would to try
to put traces on that plane too.
You've just installed a coupled inductor in series with your bus traces.
All is bad.

As I said they were short traces. Basically crossovers to help out the
autorouter.

Tam

You'll find pattern dependent errors that will drive you nutz if you're
lucky enough to find the symptom before your customer sends it back
'cause it don't work.
You can usually "get away" with some of this stuff...it's all a tradeoff.
mike


--
Return address is VALID but some sites block emails
with links. Delete this sig when replying.
.
Wanted, PCMCIA SCSI Card for HP m820 CDRW.
FS 500MHz Tek DSOscilloscope TDS540 Make Offer
Wanted 12" LCD for Compaq Armada 7770MT.
Bunch of stuff For Sale and Wanted at the link below.
MAKE THE OBVIOUS CHANGES TO THE LINK
ht<removethis>tp://www.geocities.com/SiliconValley/Monitor/4710/

 

[Terry Given]

Richard H. wrote:

In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer
signal layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the SMT
component side; or

c) a hybrid with ground layer on top, power on layer 2 (for
capacitance), and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer without
cutting up the power planes with traces. OTOH, 'b' and 'c' would
support small "escape" traces on the top layer without cutting up the
ground plane too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?

Thanks,
Richard

IME smt boards tend to be mostly-routable on the smt component layer (if
you place parts right, and suitably jiggle nets). my 4-layer pcb's have
all been made with a 2-layer inner core, I use mid-layer 1 as a solid 0V
plane (I set up via placement rules to ensure the 0V plane can flow
between all vias). This keeps the 0V plane as close as possible to the
components, maximising capacitance but minimising inductance. I am
looking at using a 6-8 layer board for my next job, specifically to
reduce the top-mid1 separation, thereby reducing L even further....

with smt boards the pads are often bigger than the components, so dense
smt boards tend to have really patchy 0V planes on the same layer, even
without interconnecting traces. I wouldnt rely on that for a ground.....

And like others have said, when done I pour an 0V plane on every layer -
better EMI performance, evens out Cu density to minimise warping etc.
from an EMI perspective, cross-hatching pours is a bad idea, and gets
worse as the cross-hatch grid gets larger.


Cheers
Terry

 

[John Popelish]

Richard H. wrote:

In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer
signal layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the SMT
component side; or

c) a hybrid with ground layer on top, power on layer 2 (for
capacitance), and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer without
cutting up the power planes with traces. OTOH, 'b' and 'c' would
support small "escape" traces on the top layer without cutting up the
ground plane too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?

Here is an example of how I made use of four layers on a recent design.

I had a small board set produced that was assembled with two of the
boards stacked up with only a small space between them. One had very
high gain, high impedance (therefore sensitive to capacitive noise)
amplifiers on it and the other had a microprocessor and some logic. I
put all the analog stuff on one side of the board with only one cross
under on the other side at the output end of the amplifier chain. It
was a nearly via-less thing of beauty. The only holes were for
connections to power and ground planes. The layer below the
amplifiers was a ground plane with its potential held half way between
the battery rails, regulated by an opamp output. The second buried
layer was split to carry both positive and negative rails. All of the
(few) logic control signals ran on the bottom layer, and connected to
the control pins of some CMOS analog switches by passing through an
island (in the signal ground layer) tied to either positive or
negative rail voltage so that they had very little capacitance to the
ground plain. This kept the ground plane very free of any high
frequency currents. One point (a fat via) on the ground plane was the
reference point (star ground) for all the high gain nodes. This
layout plan shielded the amplifiers very well from under side noise.

To keep the micro from contaminating the amplifiers, I used the two
layers on the facing side of the micro board for positive and negative
rails (there is no ground plane connection to the micro board). I
used the top and second layer for all traces on the top side and all
components are mounted there. The only sources of varying e-field on
the under side of the micro board (above the amplifiers) are a few,
small vias surrounded by supply voltage.

These boards are made in a strip and break apart. They are smaller
than a cigarette pack, so warping is not a problem.

I am very happy with the noise coupling on this set.

 

[Terry Given]

John Popelish wrote:

Richard H. wrote:

In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer
signal layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the
SMT component side; or

c) a hybrid with ground layer on top, power on layer 2 (for
capacitance), and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer
without cutting up the power planes with traces. OTOH, 'b' and 'c'
would support small "escape" traces on the top layer without cutting
up the ground plane too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?


Here is an example of how I made use of four layers on a recent design.

I had a small board set produced that was assembled with two of the
boards stacked up with only a small space between them. One had very
high gain, high impedance (therefore sensitive to capacitive noise)
amplifiers on it and the other had a microprocessor and some logic. I
put all the analog stuff on one side of the board with only one cross
under on the other side at the output end of the amplifier chain. It
was a nearly via-less thing of beauty. The only holes were for
connections to power and ground planes. The layer below the amplifiers
was a ground plane with its potential held half way between the battery
rails, regulated by an opamp output. The second buried layer was split
to carry both positive and negative rails. All of the (few) logic
control signals ran on the bottom layer, and connected to the control
pins of some CMOS analog switches by passing through an island (in the
signal ground layer) tied to either positive or negative rail voltage so
that they had very little capacitance to the ground plain. This kept the
ground plane very free of any high frequency currents. One point (a fat
via) on the ground plane was the reference point (star ground) for all
the high gain nodes. This layout plan shielded the amplifiers very well
from under side noise.

To keep the micro from contaminating the amplifiers, I used the two
layers on the facing side of the micro board for positive and negative
rails (there is no ground plane connection to the micro board). I used
the top and second layer for all traces on the top side and all
components are mounted there. The only sources of varying e-field on
the under side of the micro board (above the amplifiers) are a few,
small vias surrounded by supply voltage.

These boards are made in a strip and break apart. They are smaller than
a cigarette pack, so warping is not a problem.

I am very happy with the noise coupling on this set.

Nice, and clearly the result of a well-thought out plan.

I'm curious - did you start with any error budgeting? eg how much
capacitance can I tolerate here, etc. Or did you simply go for best
practice, then see what (if any) needed improving? Both approaches have
merits.

Cheers
Terry

 

[Guy Macon]

Terry Given wrote:

And like others have said, when done I pour an 0V plane on every layer -
better EMI performance, evens out Cu density to minimise warping etc.

...and allows the board house to etch more boards with a given amount
of chemicals. Nice to help the environment a bit while making the
board better.

 

[Mac]

On Wed, 15 Jun 2005 14:59:47 +1200, Terry Given wrote:

Richard H. wrote:
In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer
signal layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the SMT
component side; or

c) a hybrid with ground layer on top, power on layer 2 (for
capacitance), and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer without
cutting up the power planes with traces. OTOH, 'b' and 'c' would
support small "escape" traces on the top layer without cutting up the
ground plane too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?

Thanks,
Richard

IME smt boards tend to be mostly-routable on the smt component layer (if
you place parts right, and suitably jiggle nets). my 4-layer pcb's have
all been made with a 2-layer inner core, I use mid-layer 1 as a solid 0V
plane (I set up via placement rules to ensure the 0V plane can flow
between all vias). This keeps the 0V plane as close as possible to the
components, maximising capacitance but minimising inductance. I am
looking at using a 6-8 layer board for my next job, specifically to
reduce the top-mid1 separation, thereby reducing L even further....

with smt boards the pads are often bigger than the components, so dense
smt boards tend to have really patchy 0V planes on the same layer, even
without interconnecting traces. I wouldnt rely on that for a ground.....

And like others have said, when done I pour an 0V plane on every layer -
better EMI performance, evens out Cu density to minimise warping etc.
from an EMI perspective, cross-hatching pours is a bad idea, and gets
worse as the cross-hatch grid gets larger.


Cheers
Terry

I don't think cross-hatching would effect EMI performance very much, as
long as the hatches are small. But I don't really see any reason to do it,
either.

It seems to me that filling the surface layer of a SMT board with a ground
pour is inviting disaster, unless the surface layer is very lightly
routed. You are just creating a whole bunch of undesirable current paths
for ground. And you have to meticulously go around and make sure each
island is tied to the solid ground plane. And it may adversely effect the
trace impedance of surface traces.

When I designed high-density, 12-layer, single-board computers, the EMI
guys certainly never suggested that we put copper pours on the surface
layers. And these EMI guys seemed to know what they were doing.

Just my $0.02

--Mac

 

[John Popelish]

Terry Given wrote:

John Popelish wrote:

I am very happy with the noise coupling on this set.


Nice, and clearly the result of a well-thought out plan.

I'm curious - did you start with any error budgeting? eg how much
capacitance can I tolerate here, etc. Or did you simply go for best
practice, then see what (if any) needed improving? Both approaches have
merits.

All I knew was that the hand built prototype sort of worked if you
held your mouth just right and it was a Wednesday, and the first pass
layout (with little hand holding) worked fairly well, most of the
time. So this was the third attempt to prove that the circuit could
work, reliably and I pulled out every stop I could get hold of.

The only problem I am having with this layout, now is that the board
is sensitive to humidity. Evidently, the fiberglass absorbs moisture
for about a week after it is exposed to an increase in relative
humidity, and this increases the capacitance of the component pads to
the buried ground layer. This increased capacitance seems to be
nonlinear, also. Damp glass seems to be a crappy dielectric.

I am now going through various simulations with these parasitics
explicitly modeled to find out where the problem may be centered and
what alterations may minimize it.

But after a week in dry air, the present layout works just great!

 

[Terry Given]

Mac wrote:

On Wed, 15 Jun 2005 14:59:47 +1200, Terry Given wrote:


Richard H. wrote:

In a 4-layer design (<=25MHz, destined for production), what are the
"best" layers for power and ground?

a) On the 2 inner layers to improve capacitance and keep the outer
signal layers accessible;

b) on the outer layers to contain EMI, presumably with ground on the SMT
component side; or

c) a hybrid with ground layer on top, power on layer 2 (for
capacitance), and signals on layer 3 and bottom (for access)?

With 'a', I'm not sure the board can be shrunk much from 2-layer without
cutting up the power planes with traces. OTOH, 'b' and 'c' would
support small "escape" traces on the top layer without cutting up the
ground plane too badly, letting the board shrink a bit.

Thoughts? Opinions? Superstitions?

Thanks,
Richard

IME smt boards tend to be mostly-routable on the smt component layer (if
you place parts right, and suitably jiggle nets). my 4-layer pcb's have
all been made with a 2-layer inner core, I use mid-layer 1 as a solid 0V
plane (I set up via placement rules to ensure the 0V plane can flow
between all vias). This keeps the 0V plane as close as possible to the
components, maximising capacitance but minimising inductance. I am
looking at using a 6-8 layer board for my next job, specifically to
reduce the top-mid1 separation, thereby reducing L even further....

with smt boards the pads are often bigger than the components, so dense
smt boards tend to have really patchy 0V planes on the same layer, even
without interconnecting traces. I wouldnt rely on that for a ground.....

And like others have said, when done I pour an 0V plane on every layer -
better EMI performance, evens out Cu density to minimise warping etc.
from an EMI perspective, cross-hatching pours is a bad idea, and gets
worse as the cross-hatch grid gets larger.


Cheers
Terry


I don't think cross-hatching would effect EMI performance very much, as
long as the hatches are small. But I don't really see any reason to do it,
either.

depends on your definition of small. with EMI specs now up around
2-3GHz, small just got a whole lot smaller. I have seen plenty of boards
with a grid of about 5-10mm, using perhaps 0.5-1mm traces. and all of
the small bits add up, when you trace the path(s). By the time the grid
gets small enough that multiple paths cancel out the effects of
increasing distance, theres more copper than gap, so might as well pour
a plane.

It seems to me that filling the surface layer of a SMT board with a ground
pour is inviting disaster, unless the surface layer is very lightly
routed. You are just creating a whole bunch of undesirable current paths
for ground. And you have to meticulously go around and make sure each
island is tied to the solid ground plane. And it may adversely effect the
trace impedance of surface traces.

all of these things may be true on any give board. It is certainly true
that a "ground plane" is no panacaea, and that some semblance of
understanding is required.

I like to do an emc audit on my schematics, prior to layout. sort out
nets as victims or culprits, and rank in order of severity. That way I
know what to pay real close attention too, and what to ignore.

Then post-layout, do it again. what circuit have I actually built, where
are things going to go wrong etc. Chop out lumps of ground plane,
re-route traces or whatever.

then get the pcb made, and measure crosstalk, impedance etc. of all the
sensitive areas before sticking components on and really testing (if its
worth bothering. I have done on some layouts, but dont on most).

various rules-of-thumb help too. I always place bypass caps, supply and
0V vias around a chip first, then look at laying out the rest of the
parts. always using a 0V plane helps too.

When I designed high-density, 12-layer, single-board computers, the EMI
guys certainly never suggested that we put copper pours on the surface
layers. And these EMI guys seemed to know what they were doing.

Just my $0.02

--Mac

the biggest bang-for-buck is having a nice low-Z 0V (and perhaps power)
plane, that isnt chopped to fuck with traces. I havent done huge logic
boards, but the dI/dts would no doubt mandate power planes too.

when you look at the effects of shield traces vs increased separation,
separation works pretty well, esp. for a long bit of shield trace, and
you are right about the PITA of plopping vias everywhere.

OTOH analogue circuitry often likes it.

The rule-of-thumb would, I guess, be "if it doesnt hurt, pour copper
planes everywhere"

Cheers
Terry

 

[Richard H.]

Terry Given wrote:

with smt boards the pads are often bigger than the components, so dense
smt boards tend to have really patchy 0V planes on the same layer, even
without interconnecting traces. I wouldnt rely on that for a ground.....

Yep. Exactly the problem here - fine pitch, most pins used.

By the time all the traces are routed away from the chip, there's not
much room left to get 0V in there. Despite tying them together via the
bottom layer, it's coming up short.

Thanks,
Richard