3state/gate-based MUXes

[Sleep Mode]

Hi all,

I know this topic has reappeared in the past but no matter how far back
I search, I cannot find any credible posts on it. Thus, the problem:

We are implementing a complex adder design with VHDL and are
synthesizing it in the UMC90nm library (for now).

For selecting different inputs to the adder, we have come up with two
flavors per adder input (A or B),
one using i) two (one per input) 1-bit 3state buffers, and
one using ii) one 2-to-1 MUXes.

VHDL codes are straightforward, as follows:
==================================
-- Design: 3st buf

library ieee;
use ieee.std_logic_1164.all;

entity tri_state_buffer is
port(
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC_VECTOR(7 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0);
s : in STD_LOGIC_VECTOR(1 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
);
end tri_state_buffer;

architecture behavioral of tri_state_buffer is
begin
y <= a when s="00" else "ZZZZZZZZ";
y <= b when s="01" else "ZZZZZZZZ";
y <= c when s="10" else "ZZZZZZZZ";
y <= d when s="11" else "ZZZZZZZZ";
end behavioral;

==================================
-- Design: mux

library ieee;
use ieee.std_logic_1164.all;

entity mux is
port(
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
c : in STD_LOGIC_VECTOR(7 downto 0);
d : in STD_LOGIC_VECTOR(7 downto 0);
s : in STD_LOGIC_VECTOR(1 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
);
end mux;

architecture behavioral of mux is
begin
with s select
y <= a when "00",
b when "01",
c when "10",
d when others;
end behavioral;
==================================

Synthesis results indicate that the area and power of the 3states is
almost double that of the MUXes.

Which is *weird* since I was expecting the 3stated adder (due to less
adder bit-flips when inputs are in HiZ) to display better power figures
and area compared to the MUXed one.

So, the questions are:
i) Should two 3states cost LESS (area, power) than a 2-1 MUX? Up to now
I thought yes. Perhaps the UMC90 library is funny. Any clues? Could it
be that my vhdl syntax is not efficient or something?

ii) More generally, except for the fact that 3states give design tools a
hard time when debugging, is it a good practice to use 3states instead
of MUXes for *low-power* design? I have read somewhere that ASIC
professionals tend to use 3states only in buses and on chip I/Os...


Thank you all in advance for your time.

cheers,
Chris

 

[Mike Treseler]

Sleep Mode wrote:

Synthesis results indicate that the area and power of the 3states is
almost double that of the MUXes.

Maybe tri-state buffers are large.
I would only expect power savings if there were an OFF state
that got used.

Good luck.

-- Mike Treseler

 

[Paul Uiterlinden]

Sleep Mode wrote:

So, the questions are:
i) Should two 3states cost LESS (area, power) than a 2-1 MUX? Up to now
I thought yes. Perhaps the UMC90 library is funny. Any clues? Could it
be that my vhdl syntax is not efficient or something?

Have you checked the resulting schematics after synthesis? Are you really
getting tri-state buffer and muxes where you would expect them? For the
rest: I have no experience with the UMC90 library (or any library).

ii) More generally, except for the fact that 3states give design tools a
hard time when debugging, is it a good practice to use 3states instead
of MUXes for *low-power* design? I have read somewhere that ASIC
professionals tend to use 3states only in buses and on chip I/Os...

Using internal tri-state buffers cause problem after scan insertion. During
scan test contention may occur (multiple active drivers on one "wire"),
even if you have taken care that this is not possible in normal
(functional) operation mode.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.