3rd party pci dma engine

[Chad Bearden]

Is it possible to create a 3rd party pci dma engine?

I would like to dma to/from host memory to a pci device that supports
burst read/writes but has no dma hardware.

This mythical circuit would be saying "Hey! Mr Host please send a
block of data to that pci device over there." or "Hey, Mr Host grab a
block of data from that pci device and put it in your ram."

chad.

 

[Nial Stewart]

Chad Bearden <chadb@beardendesigns.com> wrote in message
news:906428f5.0310160842.420b70b8@posting.google.com...

Is it possible to create a 3rd party pci dma engine?
I would like to dma to/from host memory to a pci device that supports
burst read/writes but has no dma hardware.
This mythical circuit would be saying "Hey! Mr Host please send a
block of data to that pci device over there." or "Hey, Mr Host grab a
block of data from that pci device and put it in your ram."
chad.

You would probably have to design hardware with master functionality
to do this.

This could then grab the data in a burst from the source (as long as
it's on the same local bus, I think there might be implications
with crossing bridges) then burst write it to the destination.

Dependant on the amount of intormation to be transferred this double
action would probably be faster than the host reading the info
4 bytes at a time.


Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

 

[Assaf Sarfati]

chadb@beardendesigns.com (Chad Bearden) wrote in message news:<906428f5.0310160842.420b70b8@posting.google.com>...

Is it possible to create a 3rd party pci dma engine?

I would like to dma to/from host memory to a pci device that supports
burst read/writes but has no dma hardware.

This mythical circuit would be saying "Hey! Mr Host please send a
block of data to that pci device over there." or "Hey, Mr Host grab a
block of data from that pci device and put it in your ram."

chad.

You need a PCI master: each DMA operation reads (using PCI Master
transactions) from a source device to a FIFO, then writes (again,
using PCI Master transactions) to the destination. Both X and A have
an FPGA PCI master/target core, but its NRE is not trivial; if your
application is not intended for a large design, I'd recommend using
and off-the-shelf PCI interface chip (PLX or similar) and an FPGA
on its local-bus side. IIRC, the PLX chip even has an integrated DMA
controller between the PCI and local bus, making the FPGA much simpler
and smaller than if it had to contain a PCI core and a DMA controller.

Some additional issues: you need some sort of a DMA-Request signal
(maybe use one of the INTx# lines and mask it for the CPU's int'pt
controller?). The design would work better it you can distribute DMA
cycles and not transfer everything in one huge burst.

And finally: why not change your I/O device to one that has PCI-master
capabilities? if it's a third-party one, there are probably others with
the same functionality; if it's your own design, you can re-design it -
adding PCI Master capabilities at the source is much easier than adding
it in an additional, dedicated card.