32x1 MUX

[Xin Xiao]

I need a 32x1 Multiplexer, with each entry 8-bit-long. What's the best form
of implementation?

Currently I have more or less something like this:

type my_matrix is array (input_length - 1 downto 0) of
std_logic_vector(vect_size - 1 downto 0);

Entity vmux is
generic(
vect_size : integer := 8;
input_length : integer := 32;
sel_length : integer := 5
);

port ( muxin : in my_matrix;
muxout : out std_logic_vector(vect_size - 1 downto 0);
sel : in std_logic_vector(sel_length - 1 downto 0)
);
end vmux;

Architecture A_vmux of vmux is

begin
muxout <= muxin(to_integer(unsigned(sel)));
end A_vmux;

Do you know other possible ways to implement my mux?

 

[Pieter Hulshoff]

Xin Xiao wrote:

I need a 32x1 Multiplexer, with each entry 8-bit-long. What's the best
form of implementation?

Currently I have more or less something like this:

type my_matrix is array (input_length - 1 downto 0) of
std_logic_vector(vect_size - 1 downto 0);

Entity vmux is
generic(
vect_size : integer := 8;
input_length : integer := 32;
sel_length : integer := 5
);

port ( muxin : in my_matrix;
muxout : out std_logic_vector(vect_size - 1 downto 0);
sel : in std_logic_vector(sel_length - 1 downto 0)
);
end vmux;

Architecture A_vmux of vmux is

begin
muxout <= muxin(to_integer(unsigned(sel)));
end A_vmux;

Do you know other possible ways to implement my mux?

I presume you mean from a synthesis point of view? Depends a bit on if you want
to use the code for an FPGA or for an ASIC. We've noticed in the past that
Synopsis has a serious problem with multiplexers, and you actually have to tell
Synopsis directly that you wish to use a multiplexer in your end logic. For that
you create a separate mux block that you synthesize, and then instantiate
depending on your needs (using FOR ... GENERATE statements).

Kind regards,

Pieter Hulshoff