D
dhrumil
Guest
Can any one help me in writing the 32 bit unsigned multiplication in
verilog. I know that * can be used but it takes 32 cycles to complete
the calculation. Is there anyway to do in less clk cycles and also
less area during synthesis.
I also implemented the booth algorithm but it also takes 8 clk cycles
for 8 bit nos. I can use the while loop to make it synthesizable.
module boothmulti(ans,a,b);
input [7:0]a,b;
output [16:1]ans;
reg [16:1]ans;
reg [16:0]temp;
integer i;
always @(a or b)
begin
temp[0]=0;
temp[16:9]=4'b0;
temp[8:1]=a;
for(i=0;i<8;i=i+1)
begin
if (temp[1:0] == 2'b01)
begin
temp[16:9] = temp[16:9] +b;
temp = temp >> 1;
temp[16]=temp[15];
end
else if (temp[1:0]==2'b10)
begin
temp[16:9] = temp[16:9] - b;
temp = temp >> 1;
temp[16]=temp[15];
end
else if (temp[1:0]==2'b11)
begin
temp = temp >> 1;
temp[16]=temp[15];
end
else
begin
temp = temp >> 1;
temp[16]=temp[15];
end
end
ans[16:1]= temp[16:1];
end
endmodule
any help would be appreciated.
Thanks,
verilog. I know that * can be used but it takes 32 cycles to complete
the calculation. Is there anyway to do in less clk cycles and also
less area during synthesis.
I also implemented the booth algorithm but it also takes 8 clk cycles
for 8 bit nos. I can use the while loop to make it synthesizable.
module boothmulti(ans,a,b);
input [7:0]a,b;
output [16:1]ans;
reg [16:1]ans;
reg [16:0]temp;
integer i;
always @(a or b)
begin
temp[0]=0;
temp[16:9]=4'b0;
temp[8:1]=a;
for(i=0;i<8;i=i+1)
begin
if (temp[1:0] == 2'b01)
begin
temp[16:9] = temp[16:9] +b;
temp = temp >> 1;
temp[16]=temp[15];
end
else if (temp[1:0]==2'b10)
begin
temp[16:9] = temp[16:9] - b;
temp = temp >> 1;
temp[16]=temp[15];
end
else if (temp[1:0]==2'b11)
begin
temp = temp >> 1;
temp[16]=temp[15];
end
else
begin
temp = temp >> 1;
temp[16]=temp[15];
end
end
ans[16:1]= temp[16:1];
end
endmodule
any help would be appreciated.
Thanks,