30khz from 1Mhz

[trescot@gmail.com]

Hi guys,

I have a design question.
Any idea how can I generate a 32 kHZ clock from 1Mhz clock source ? It
doesn't have to be exactly accurate.


Thanks

 

[Mike Lewis]

<trescot@gmail.com> wrote in message
news:1190923488.283062.295530@w3g2000hsg.googlegroups.com...

Hi guys,

I have a design question.
Any idea how can I generate a 32 kHZ clock from 1Mhz clock source ? It
doesn't have to be exactly accurate.


Thanks

\

A divide by 31 counter design gets close ... how close do you need to be?

Mike

 

[John_H]

<trescot@gmail.com> wrote in message
news:1190923488.283062.295530@w3g2000hsg.googlegroups.com...

Hi guys,

I have a design question.
Any idea how can I generate a 32 kHZ clock from 1Mhz clock source ? It
doesn't have to be exactly accurate.


Thanks

If you don't mind your pulse widths alternating between 15 and 16 us, this
code gives precisely 32 kHz as measured with a frequency meter.

reg [8:0] accum;
always @(posedge clk) // 8/125 == 32/1000
accum <= accum + (accum[6] ? 8'd139 : 8'd8); // 139 is 256-125+8

wire my32kHz = accum[8];

 

[John_H]

John_H wrote:

trescot@gmail.com> wrote in message
news:1190923488.283062.295530@w3g2000hsg.googlegroups.com...
Hi guys,

I have a design question.
Any idea how can I generate a 32 kHZ clock from 1Mhz clock source ? It
doesn't have to be exactly accurate.


Thanks

If you don't mind your pulse widths alternating between 15 and 16 us, this
code gives precisely 32 kHz as measured with a frequency meter.

reg [8:0] accum;
always @(posedge clk) // 8/125 == 32/1000
accum <= accum + (accum[6] ? 8'd139 : 8'd8); // 139 is 256-125+8

wire my32kHz = accum[8];

Your subject line read 30 kHz. The note read 32 kHz. Many applications
want 32768 Hz. The snippet I included above is for 32 kHz.

 

[trescot@gmail.com]

On Sep 27, 9:35 pm, John_H <newsgr...@johnhandwork.com> wrote:

John_H wrote:
tres...@gmail.com> wrote in message
news:1190923488.283062.295530@w3g2000hsg.googlegroups.com...
Hi guys,

I have a design question.
Any idea how can I generate a 32 kHZ clock from 1Mhz clock source ? It
doesn't have to be exactly accurate.

Thanks

If you don't mind your pulse widths alternating between 15 and 16 us, this
code gives precisely 32 kHz as measured with a frequency meter.

reg [8:0] accum;
always @(posedge clk) // 8/125 == 32/1000
accum <= accum + (accum[6] ? 8'd139 : 8'd8); // 139 is 256-125+8

wire my32kHz = accum[8];

Your subject line read 30 kHz. The note read 32 kHz. Many applications
want 32768 Hz. The snippet I included above is for 32 kHz.

Thanks guys.

John, you are right I need 32khz clock because I have many application
operating at that frequency.
But can you be a bit explicit how you generated it?

 

[John_H]

<trescot@gmail.com> wrote in message
news:1190993905.396977.309440@d55g2000hsg.googlegroups.com...

Thanks guys.

John, you are right I need 32khz clock because I have many application
operating at that frequency.
But can you be a bit explicit how you generated it?

The code snippit uses an approach called Direct Digital Synthesis (DDS)
where an accumlator is used instead of a divider to allow an effective
fractional frequency ratio. Most DDS implementations use a large
accumulator to guarantee some level of frequency accuracy. The code I
provided has a small twist: a modulus that isn't a power of 2.

Since you want 32 kHz from 1 MHz, you want a frequency ratio of 32/1000 or
4/125. The DDS will give you one pulse every 31 or 32 input clocks. If you
want a square-wave output, these pulses need to be at twice the frequency
(8/125 frequency ratio) used to toggle a register. I integrated these into
one vector. Where the 125 modulus needs 7 bits, the 8th bit is used to
generate the overflow bit. This overflow bit is used to make the adjustment
fot the non 2^n modulus. In the snippet, the main line (oops! I had a
typo - the bit should be accum[7], not [6])

accum <= accum + (accum[7] ? 8'd139 : 8'd8); // 139 is 256-125+8

uses the overflow bit at bit 7 to both clear the bit and adjust for the
modulus (256-125) while still adding the phase accumulation value of 8 for
the overall 8/125 toggle rate. The MSbit at accum[8] is the resulting
square wave.

Every input cycle adds 8. Every output cycle has a range of 125 thanks to
the modulus adjustment. The exact frequency is attained without large
accumulators. This any-modulus DDS approach is only limited by the
accumulator speed allowing very high FPGA speeds if you ever find yourself
very far from your current 1 MHz rate.

For your frequency ratio, normal DDS would give you 2.4% inaccuracy for 5-9
bits, 0.8% inaccuracy for 10-11 bits, around .05% inaccuracy for 12-15 bits,
and improvements as you add bits to the accumulator. The variable modulus
is very FPGA friendly for selecting between the two constants and gives 100%
accuracy relative to your input frequency.

- John_H

 

[gabor]

On Sep 28, 1:23 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

tres...@gmail.com> wrote in message

news:1190993905.396977.309440@d55g2000hsg.googlegroups.com...



Thanks guys.

John, you are right I need 32khz clock because I have many application
operating at that frequency.
But can you be a bit explicit how you generated it?

The code snippit uses an approach called Direct Digital Synthesis (DDS)
where an accumlator is used instead of a divider to allow an effective
fractional frequency ratio. Most DDS implementations use a large
accumulator to guarantee some level of frequency accuracy. The code I
provided has a small twist: a modulus that isn't a power of 2.

Since you want 32 kHz from 1 MHz, you want a frequency ratio of 32/1000 or
4/125. The DDS will give you one pulse every 31 or 32 input clocks. If you
want a square-wave output, these pulses need to be at twice the frequency
(8/125 frequency ratio) used to toggle a register. I integrated these into
one vector. Where the 125 modulus needs 7 bits, the 8th bit is used to
generate the overflow bit. This overflow bit is used to make the adjustment
fot the non 2^n modulus. In the snippet, the main line (oops! I had a
typo - the bit should be accum[7], not [6])

accum <= accum + (accum[7] ? 8'd139 : 8'd8); // 139 is 256-125+8

uses the overflow bit at bit 7 to both clear the bit and adjust for the
modulus (256-125) while still adding the phase accumulation value of 8 for
the overall 8/125 toggle rate. The MSbit at accum[8] is the resulting
square wave.

Every input cycle adds 8. Every output cycle has a range of 125 thanks to
the modulus adjustment. The exact frequency is attained without large
accumulators. This any-modulus DDS approach is only limited by the
accumulator speed allowing very high FPGA speeds if you ever find yourself
very far from your current 1 MHz rate.

For your frequency ratio, normal DDS would give you 2.4% inaccuracy for 5-9
bits, 0.8% inaccuracy for 10-11 bits, around .05% inaccuracy for 12-15 bits,
and improvements as you add bits to the accumulator. The variable modulus
is very FPGA friendly for selecting between the two constants and gives 100%
accuracy relative to your input frequency.

- John_H

See also the recent thread "Frequency synthesis" in this newsgroup...