3 to 1 mux with 4 bit inputs

Guest
Hi all,

I'm learning Verilog. Trying to design a multiplexer:

module vector_net_multiplexer_tb;

reg [3:0] input1, input2, input3, sel_ip;
reg [1:0] sel;

initial
begin
$dumpfile ("vector_net_multiplexer_tb.vcd");
$dumpvars (1, vector_net_multiplexer_tb);
$monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",
input1, input2, input3, sel, sel_ip);

sel = 2'b00;
input1 = 4'b1010;
input2 = 4'b1100;
input3 = 4'b0110;

#5 sel = 2'b01;
#10 sel = 2'b10;
#15 sel = 2'b11;
#20 sel = 2'b10;
#25 $finish;
end

vector_net_multiplexer mux0 (
.input1(input1),
.input2(input2),
.input3(input3),
.sel(.sel),
.sel_ip(sel_ip)
);


endmodule // vector_net_multiplexer_tb



module vector_net_multiplexer(
//inputs
input [3:0] input1,
input [3:0] input2,
input [3:0] input3,

input [1:0] sel,

//output
output [3:0] sel_ip
);
reg sel_ip;
reg sel;

always @ ( input1 or input2 or input3 or sel)
begin
case (sel)
2'b00:
sel_ip = input1;
2'b01:
sel_ip = input2;
2'b10:
sel_ip = input3;
2'b11:
sel_ip = input1;
endcase // case (sel)
end

endmodule // vector_net_multiplexer




compiling with icarus verilog gives:

iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v
vector_net_multiplexer_tb.v:29: syntax error
vector_net_multiplexer_tb.v:29: error: invalid port connection expression.


Can someone tell me what the problem is?

Thanks,
asp5
 
Am Dienstag, 31. Juli 2012 07:42:49 UTC+2 schrieb asp...@gmail.com:
Hi all,



I'm learning Verilog. Trying to design a multiplexer:



module vector_net_multiplexer_tb;



reg [3:0] input1, input2, input3, sel_ip;

reg [1:0] sel;



initial

begin

$dumpfile ("vector_net_multiplexer_tb.vcd");

$dumpvars (1, vector_net_multiplexer_tb);

$monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",

input1, input2, input3, sel, sel_ip);



sel = 2'b00;

input1 = 4'b1010;

input2 = 4'b1100;

input3 = 4'b0110;



#5 sel = 2'b01;

#10 sel = 2'b10;

#15 sel = 2'b11;

#20 sel = 2'b10;

#25 $finish;

end



vector_net_multiplexer mux0 (

.input1(input1),

.input2(input2),

.input3(input3),

.sel(.sel),

.sel_ip(sel_ip)

);





endmodule // vector_net_multiplexer_tb







module vector_net_multiplexer(

//inputs

input [3:0] input1,

input [3:0] input2,

input [3:0] input3,



input [1:0] sel,



//output

output [3:0] sel_ip

);

reg sel_ip;

reg sel;



always @ ( input1 or input2 or input3 or sel)

begin

case (sel)

2'b00:

sel_ip = input1;

2'b01:

sel_ip = input2;

2'b10:

sel_ip = input3;

2'b11:

sel_ip = input1;

endcase // case (sel)

end



endmodule // vector_net_multiplexer









compiling with icarus verilog gives:



iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v

vector_net_multiplexer_tb.v:29: syntax error

vector_net_multiplexer_tb.v:29: error: invalid port connection expression.





Can someone tell me what the problem is?



Thanks,

asp5
Click to expand...
Hi,
one dot too much in line 29:
.sel(.sel),
^

Have a nice synthesis
Eilert
 
Am Dienstag, 31. Juli 2012 07:42:49 UTC+2 schrieb asp...@gmail.com:
Hi all,



I'm learning Verilog. Trying to design a multiplexer:



module vector_net_multiplexer_tb;



reg [3:0] input1, input2, input3, sel_ip;

reg [1:0] sel;



initial

begin

$dumpfile ("vector_net_multiplexer_tb.vcd");

$dumpvars (1, vector_net_multiplexer_tb);

$monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",

input1, input2, input3, sel, sel_ip);



sel = 2'b00;

input1 = 4'b1010;

input2 = 4'b1100;

input3 = 4'b0110;



#5 sel = 2'b01;

#10 sel = 2'b10;

#15 sel = 2'b11;

#20 sel = 2'b10;

#25 $finish;

end



vector_net_multiplexer mux0 (

.input1(input1),

.input2(input2),

.input3(input3),

.sel(.sel),

.sel_ip(sel_ip)

);





endmodule // vector_net_multiplexer_tb







module vector_net_multiplexer(

//inputs

input [3:0] input1,

input [3:0] input2,

input [3:0] input3,



input [1:0] sel,



//output

output [3:0] sel_ip

);

reg sel_ip;

reg sel;



always @ ( input1 or input2 or input3 or sel)

begin

case (sel)

2'b00:

sel_ip = input1;

2'b01:

sel_ip = input2;

2'b10:

sel_ip = input3;

2'b11:

sel_ip = input1;

endcase // case (sel)

end



endmodule // vector_net_multiplexer









compiling with icarus verilog gives:



iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v

vector_net_multiplexer_tb.v:29: syntax error

vector_net_multiplexer_tb.v:29: error: invalid port connection expression.





Can someone tell me what the problem is?



Thanks,

asp5
Click to expand...
Hi,
one dot too much in line 29:
.sel(.sel),
^

Have a nice synthesis
Eilert
 
On Monday, July 30, 2012 11:15:43 PM UTC-7, (unknown) wrote:
Am Dienstag, 31. Juli 2012 07:42:49 UTC+2 schrieb asp...@gmail.com:

Hi all,







I'm learning Verilog. Trying to design a multiplexer:







module vector_net_multiplexer_tb;







reg [3:0] input1, input2, input3, sel_ip;



reg [1:0] sel;







initial



begin



$dumpfile ("vector_net_multiplexer_tb.vcd");



$dumpvars (1, vector_net_multiplexer_tb);



$monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",



input1, input2, input3, sel, sel_ip);







sel = 2'b00;



input1 = 4'b1010;



input2 = 4'b1100;



input3 = 4'b0110;







#5 sel = 2'b01;



#10 sel = 2'b10;



#15 sel = 2'b11;



#20 sel = 2'b10;



#25 $finish;



end







vector_net_multiplexer mux0 (



.input1(input1),



.input2(input2),



.input3(input3),



.sel(.sel),



.sel_ip(sel_ip)



);











endmodule // vector_net_multiplexer_tb















module vector_net_multiplexer(



//inputs



input [3:0] input1,



input [3:0] input2,



input [3:0] input3,







input [1:0] sel,







//output



output [3:0] sel_ip



);



reg sel_ip;



reg sel;







always @ ( input1 or input2 or input3 or sel)



begin



case (sel)



2'b00:



sel_ip = input1;



2'b01:



sel_ip = input2;



2'b10:



sel_ip = input3;



2'b11:



sel_ip = input1;



endcase // case (sel)



end







endmodule // vector_net_multiplexer



















compiling with icarus verilog gives:







iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v



vector_net_multiplexer_tb.v:29: syntax error



vector_net_multiplexer_tb.v:29: error: invalid port connection expression.











Can someone tell me what the problem is?







Thanks,



asp5



Hi,

one dot too much in line 29:

.sel(.sel),

^



Have a nice synthesis

Eilert
Click to expand...
Thanks Eilert. Did not notice this :)
 
asp654@gmail.com wrote:

(snip)

module vector_net_multiplexer(
//inputs
input [3:0] input1,
input [3:0] input2,
input [3:0] input3,

input [1:0] sel,

//output
output [3:0] sel_ip
);
reg sel_ip;
reg sel;
Click to expand...
I don't think this is the reason for the message, but I
wouldn't have made sel a reg. Maybe it doesn't matter, though.

always @ ( input1 or input2 or input3 or sel)
begin
case (sel)
2'b00:
sel_ip = input1;
2'b01:
sel_ip = input2;
2'b10:
sel_ip = input3;
2'b11:
sel_ip = input1;
endcase // case (sel)
end

endmodule // vector_net_multiplexer
Click to expand...
-- glen
 
goouse99@googlemail.com wrote:
Am Dienstag, 31. Juli 2012 07:42:49 UTC+2 schrieb asp...@gmail.com:
Hi all,



I'm learning Verilog. Trying to design a multiplexer:



module vector_net_multiplexer_tb;



reg [3:0] input1, input2, input3, sel_ip;

reg [1:0] sel;



initial

begin

$dumpfile ("vector_net_multiplexer_tb.vcd");

$dumpvars (1, vector_net_multiplexer_tb);

$monitor ("input1 = %b, input2 = %b, input3 = %b, sel = %b, sel_ip = %b",

input1, input2, input3, sel, sel_ip);



sel = 2'b00;

input1 = 4'b1010;

input2 = 4'b1100;

input3 = 4'b0110;



#5 sel = 2'b01;

#10 sel = 2'b10;

#15 sel = 2'b11;

#20 sel = 2'b10;

#25 $finish;

end



vector_net_multiplexer mux0 (

.input1(input1),

.input2(input2),

.input3(input3),

.sel(.sel),

.sel_ip(sel_ip)

);





endmodule // vector_net_multiplexer_tb







module vector_net_multiplexer(

//inputs

input [3:0] input1,

input [3:0] input2,

input [3:0] input3,



input [1:0] sel,



//output

output [3:0] sel_ip

);

reg sel_ip;

reg sel;



always @ ( input1 or input2 or input3 or sel)

begin

case (sel)

2'b00:

sel_ip = input1;

2'b01:

sel_ip = input2;

2'b10:

sel_ip = input3;

2'b11:

sel_ip = input1;

endcase // case (sel)

end



endmodule // vector_net_multiplexer









compiling with icarus verilog gives:



iverilog -o vector_net_multiplexer vector_net_multiplexer.v vector_net_multiplexer_tb.v

vector_net_multiplexer_tb.v:29: syntax error

vector_net_multiplexer_tb.v:29: error: invalid port connection expression.





Can someone tell me what the problem is?



Thanks,

asp5

Hi,
one dot too much in line 29:
.sel(.sel),
^

Have a nice synthesis
Eilert
Click to expand...
It also looks like you might mis-understand the operation of the delays:

#5 sel = 2'b01;
#10 sel = 2'b10;
#15 sel = 2'b11;
#20 sel = 2'b10;
#25 $finish;

Each of the #delays adds to the previous delay, so you will
wait 5 units (usually ns, but it depends on `timescale) then
another 10 units, then another 15 units, etc. If you want to
use absolute times, then you need to either use non-blocking
assignments (this gets a bit hairy) or place each in its own
initial block.

-- Gabor
 
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