3-dimensional memory is not working in VERILOG-XL plzzzzzzz

[linuxczar]

hi in previous post i did posted wrong test bench. excuse me

//module for testing 2-dimensional memory
module rom_2d(rom_data,rom_row,rom_col);
output [3:0] rom_data;
input [1:0] rom_row,rom_col;
reg [3:0] rom[3:0][3:0];


assign rom_data=rom[rom_row][rom_col];

initial
begin
rom[0][0]=4'd4;rom[0][1]=4'd10;rom[0][2]=4'd9;rom[0][3]=4'd2;
rom[1][0]=4'd2;rom[1][1]=4'd14;rom[1][2]=4'd3;rom[1][3]=4'd6;
rom[2][0]=4'd13;rom[2][1]=4'd11;rom[2][2]=4'd9;rom[2][3]=4'd7;
rom[3][0]=4'd15;rom[3][1]=4'd12;rom[3][2]=4'10;rom[3][3]=4'd11;
end
endmodule

test bench

//testbench for rom_2d.v
module rom_2d;
reg [1:0] rom_row,rom_col;
wire [3:0] rom_data;

rom_2d rm(rom_data,rom_row,rom_col);

initial
begin
$monitor($time,"rom_data=%d----rom_row=%d,rom_col=
%d",rom_data,rom_row,rom_col);
end

initial
begin
rom_row=2'd0;rom_col=2'd0;
#10 rom_row=2'd0;rom_col=2'd0;
#10 rom_row=2'd2;rom_col=2'd1;
#10 rom_row=2'd2;rom_col=2'd3;
#10 rom_row=2'd3;rom_col=2'd1;
#10 rom_row=2'd1;rom_col=2'd2;
end


initial
begin
$recordfile("rom_2d.trn");
$recordvars();
end
endmodule

messages i am getting in VERILOG-XL are

Compiling source file "rom_2d.v"

Error! syntax error
[Verilog]
"rom_2d.v", 5: reg [3:0] rom[3:0][<-

Error! syntax error
[Verilog]
"rom_2d.v", 8: assign rom_data=rom[rom_row] [<-

Error! syntax error
[Verilog]
"rom_2d.v", 12: rom[0][<-
3 errors
End of Tool: VERILOG-XL 05.60.001-p Apr 12, 2007 02:11:56


thanks and regards
gkreddybh