3-dimensional memory is not working in VERILOG-XL plzzzzzzz

[linuxczar]

hi
the following are module for 3-dimensional memory in verilog

//module for testing 2-dimensional memory
module rom_2d(rom_data,rom_row,rom_col);
output [3:0] rom_data;
input [1:0] rom_row,rom_col;
reg [3:0] rom[3:0][3:0];


assign rom_data=rom[rom_row][rom_col];

initial
begin
rom[0][0]=4'd4;rom[0][1]=4'd10;rom[0][2]=4'd9;rom[0][3]=4'd2;
rom[1][0]=4'd2;rom[1][1]=4'd14;rom[1][2]=4'd3;rom[1][3]=4'd6;
rom[2][0]=4'd13;rom[2][1]=4'd11;rom[2][2]=4'd9;rom[2][3]=4'd7;
rom[3][0]=4'd15;rom[3][1]=4'd12;rom[3][2]=4'10;rom[3][3]=4'd11;
end
endmodule

ofcourse,rightnow i didn't added enable signals. first i want to test
it
but the following error message is coming in VERILOG-XL

Compiling source file "rom_2d.v"

Error! syntax error
[Verilog]
"rom_2d.v", 5: reg [3:0] rom[3:0][<-

Error! syntax error
[Verilog]
"rom_2d.v", 8: assign rom_data=rom[rom_row] [<-

Error! syntax error
[Verilog]
"rom_2d.v", 12: rom[0][<-
3 errors
End of Tool: VERILOG-XL 05.60.001-p Apr 12, 2007 02:11:56


test bench is as follows

//testbench for rom.v
module rom_tb;
reg [3:0] rom_addr;
wire [3:0] rom_data;

rom_bcd rmbd(rom_data,rom_addr);

initial
begin
$monitor($time,"rom_data=%d---rom_addr=%d",rom_data,rom_addr);
end

initial
begin
rom_addr=4'd0;
#10 rom_addr=4'd2;
#10 rom_addr=4'd8;
#10 rom_addr=4'd12;
#10 rom_addr=4'd10;
end

initial
begin
$recordfile("rom.trn");
$recordvars();
end
endmodule


i am in urgent.plz drag out of this

thanks and regards
gkreddybh

 

[Jonathan Bromley]

On 11 Apr 2007 13:51:23 -0700, "linuxczar"
<h.264world@gmail.com> wrote:

the following are module for 3-dimensional memory in verilog
[...]
but the following error message is coming in VERILOG-XL

I don't think Verilog-XL supports the new multi-dimensional array
stuff - or, indeed, anything much of Verilog-2001. However, I
could be wrong. Try looking carefully at the man pages or other
help docs for any command line switches to enable Verilog-2001
language constructs.

If you have it installed, try using the "ncverilog" command
in place of "verilog". It uses the NC compiler, but runs
Verilog compile/elaborate/execute in a single step
just like good old Verilog-XL.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

Jonathan Bromley wrote:

I don't think Verilog-XL supports the new multi-dimensional array
stuff - or, indeed, anything much of Verilog-2001.

Jonathan is correct. Verilog-XL does support signed arithmetic, but
that was implemented before it was standardized in Verilog-2001.
I think that is about it.

 

[linuxczar]

On Apr 12, 6:50 am, s...@cadence.com wrote:

Jonathan Bromley wrote:

I don't think Verilog-XL supports the new multi-dimensional array
stuff - or, indeed, anything much of Verilog-2001.

Jonathan is correct. Verilog-XL does support signed arithmetic, but
that was implemented before it was standardized in Verilog-2001.
I think that is about it.

yeah it's working with "ncverilog"
thank you Jonathan
regards
gkreddybh