3 bit message detector

[Mahurshi Akilla]

hey guys, i am pasting a simple 3 bit message detector (detects 100)
code that i wrote a while ago for fun. i was wondering if you guys
could suggest any improvements to the code in terms of coding style
and things of that nature. any comments/feedback is appreciated.
thanks

`timescale 1ns / 1ps
`define MESSAGE 3'b100
module detector(Din, Reset, clk, Flag);
input Din;
input Reset;
input clk;
output Flag;

reg [2:0] message;
reg Flag;

always @ (posedge clk or posedge Reset)
begin

if (Reset == 1'b1)
begin
message <= 3'b000;
Flag <= 0;
end
else
begin
message <= message << 1;
message[0] <= Din;

if (message == `MESSAGE)
begin
Flag <= 1;
end
else
begin
Flag <= 0;
end
end
$display("reset = %d, din = %d, message = %b, flag = %d", Reset, Din,
message, Flag);

end

endmodule


Mahurshi Akilla

 

[John_H]

Mahurshi Akilla wrote:

hey guys, i am pasting a simple 3 bit message detector (detects 100)
code that i wrote a while ago for fun. i was wondering if you guys
could suggest any improvements to the code in terms of coding style
and things of that nature. any comments/feedback is appreciated.
thanks

`timescale 1ns / 1ps
`define MESSAGE 3'b100
module detector(Din, Reset, clk, Flag);
input Din;
input Reset;
input clk;
output Flag;

reg [2:0] message;
reg Flag;

always @ (posedge clk or posedge Reset)
begin

if (Reset == 1'b1)
begin
message <= 3'b000;
Flag <= 0;
end
else
begin
message <= message << 1;
message[0] <= Din;

if (message == `MESSAGE)
begin
Flag <= 1;
end
else
begin
Flag <= 0;
end
end
$display("reset = %d, din = %d, message = %b, flag = %d", Reset, Din,
message, Flag);

end

endmodule


Mahurshi Akilla

My suggestion-by-example would include in-line directives, 2-space
indenting, lining up of declaration names and assignment operators where
convenient, 1'b0 rather than 0 style assignments, and inline assignment
of a conditional to the Flag. And NEVER use tabs! They just don't
transport from editor to editor. If you didn't have the $display, you
wouldn't need the begin/end lines of the always block. This is my
opinion; the more things line up the easier it is to read. Even the
commas in the port declaration is unusual to see (given to code from
other authors I've seen) but it gives a continuity of the declaration
list; module instantiations are similar in feel. The short indenting
gives room for comments without going over a reasonable line length (I
use 96 character maximum unless a higher value is warranted.

`timescale 1ns / 1ps
`define MESSAGE 3'b100
module
detector
( input Din
, input Reset
, input clk
, output Flag
);

reg [2:0] message;
reg Flag;

always @(posedge clk or posedge Reset)
begin
if( Reset )
begin
message <= 3'b000;
Flag <= 0;
end
else
begin
message <= {message, Din};
Flag <= message == `MESSAGE;
end
$display("reset = %d, din = %d, message = %b, flag = %d", Reset, Din,
message, Flag);

end

endmodule

 

[Alex]

On Apr 9, 9:03 pm, John_H <newsgr...@johnhandwork.com> wrote:

Mahurshi Akilla wrote:
hey guys, i am pasting a simple 3 bit message detector (detects 100)
code that i wrote a while ago for fun. i was wondering if you guys
could suggest any improvements to the code in terms of coding style
and things of that nature. any comments/feedback is appreciated.
thanks

`timescale 1ns / 1ps
`define MESSAGE 3'b100
module detector(Din, Reset, clk, Flag);
input Din;
input Reset;
input clk;
output Flag;

reg [2:0] message;
reg Flag;

always @ (posedge clk or posedge Reset)
begin

if (Reset == 1'b1)
begin
message <= 3'b000;
Flag <= 0;
end
else
begin
message <= message << 1;
message[0] <= Din;

if (message == `MESSAGE)
begin
Flag <= 1;
end
else
begin
Flag <= 0;
end
end
$display("reset = %d, din = %d, message = %b, flag = %d", Reset, Din,
message, Flag);

end

endmodule

Mahurshi Akilla

My suggestion-by-example would include in-line directives, 2-space
indenting, lining up of declaration names and assignment operators where
convenient, 1'b0 rather than 0 style assignments, and inline assignment
of a conditional to the Flag. And NEVER use tabs! They just don't
transport from editor to editor. If you didn't have the $display, you
wouldn't need the begin/end lines of the always block. This is my
opinion; the more things line up the easier it is to read. Even the
commas in the port declaration is unusual to see (given to code from
other authors I've seen) but it gives a continuity of the declaration
list; module instantiations are similar in feel. The short indenting
gives room for comments without going over a reasonable line length (I
use 96 character maximum unless a higher value is warranted.

`timescale 1ns / 1ps
`define MESSAGE 3'b100
module
detector
( input Din
, input Reset
, input clk
, output Flag
);

reg [2:0] message;
reg Flag;

always @(posedge clk or posedge Reset)
begin
if( Reset )
begin
message <= 3'b000;
Flag <= 0;
end
else
begin
message <= {message, Din};
Flag <= message == `MESSAGE;
end
$display("reset = %d, din = %d, message = %b, flag = %d", Reset, Din,
message, Flag);

end

endmodule- Hide quoted text -

- Show quoted text -

To match all kinds of patterns, it makes sense to create reusable
design component.
The library of well-thinked and properly verified design components
may greatly help you in design process.

Here is an example of "pmatch" design component with the testbench:

//--------------------------------------------------
module pmatch (clk, rst_n, din, pattern, match);
parameter BWIDTH = 4;

input clk, rst_n, din;
input [BWIDTH-1:0] pattern;
output match;

reg [BWIDTH-1:0] pattern_reg;

always @(posedge clk or negedge rst_n)
if (!rst_n) pattern_reg <= {BWIDTH{1'b0}};
else pattern_reg <= {pattern_reg,din};

assign match = pattern_reg == pattern;

endmodule

//--------------------------------------------------

module pmatch_test;
reg clk = 0;
always #5 clk <= ~clk;

reg rst_n = 0;
initial #20 rst_n = 1;

reg din = 0;
always @(posedge clk) if (rst_n)
din <= {$random}%100 < 10;

pmatch #3 p1 (clk, rst_n, din, 3'b100, match);

initial begin
$dumpvars;
$monitor ($time, "match = %b", match);
#2000 $finish;
end

endmodule

-Alex