2x Clock Multiplier Help

[GamEmpire]

Hi All,

Been trying to get a clock multiplier working for a CPU project I am
working on, but I've had little luck.

http://i41.tinypic.com/ivuzvs.png is basically what I need to do.

Basically, I need to create a module to double the input clock speed.
I found a way to do this, but it is not synthesizeable with synopsys.

Current Code is:

module cu_timer(clk, reset, clk2);
input clk, reset;
output clk2;
reg clk2;
wire w1;

assign w1 = ~clk;

always @ (posedge w1 or negedge reset)
begin

clk2 <= (reset) ? ~clk2 : 0;

end
endmodule


The error I get while synthesizing is: Error: ./src/cu_timer.v:16:
Cannot test variable 'reset' because it was not in the event
expression or with wrong polarity. (ELAB-300)

You can see the manual page for this error here http://i39.tinypic.com/4v4c39.png
(I couldn't copy and paste out of my x11 window for some reason).

If anyone has any ideas on how to make this synthesizeable, that would
be greatly appreciated.

-Josh

 

[Muzaffer Kal]

On Tue, 31 Mar 2009 17:30:10 -0700 (PDT), GamEmpire
<gamempire@gmail.com> wrote:

Hi All,

Been trying to get a clock multiplier working for a CPU project I am
working on, but I've had little luck.

http://i41.tinypic.com/ivuzvs.png is basically what I need to do.

Basically, I need to create a module to double the input clock speed.
I found a way to do this, but it is not synthesizeable with synopsys.

Current Code is:

module cu_timer(clk, reset, clk2);
input clk, reset;
output clk2;
reg clk2;
wire w1;

assign w1 = ~clk;

always @ (posedge w1 or negedge reset)
begin

clk2 <= (reset) ? ~clk2 : 0;

end
endmodule


The error I get while synthesizing is: Error: ./src/cu_timer.v:16:
Cannot test variable 'reset' because it was not in the event
expression or with wrong polarity. (ELAB-300)

You can see the manual page for this error here http://i39.tinypic.com/4v4c39.png
(I couldn't copy and paste out of my x11 window for some reason).

If anyone has any ideas on how to make this synthesizeable, that would
be greatly appreciated.

-Josh

You are asking for a clock doubler/multiplier but you picture and your
logic suggests that you're trying to get a divided clock. If you
really want a divide by 2 clock as your logic suggests, that's easy.
However you can't easily multiply your clock by two.
Assuming you want a divider, you just need to fix your logic as
follows to make it synthesizable:

always @ (posedge w1 or negedge reset)
begin
if (!reset)
clk2 <= 0;
else
clk2 <= ~clk2;
end

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

 

[hairyotter]

Hi Josh,

In your always you declare for negedge reset, so you're telling the
compiler that you want the always block to be entered when reset=1'b0

However, your code tests for "reset ?", which means reset = 1'b1

Try doing
clk2 <= (!reset) ? 0 : ~clk2;

What version of synopsys are you using ?

In any case Kal's code snippet is more elegant and is the way flops
are usually described and he's right, what you're describing is a
clock divider, not doubler.

Ciao, Marco.