2 modules

[pat]

i have 2 modules.
one i call 'main'
one is called 'counter' which is instantiated in main.

main has...
clk input
counter_input
[7:0] output

counter has...
clk input
counter output

(i am using xilinx web pack verilog design (not schematic design)

i instantiate counter in main sending it clk only. inside counter i
have always @(posedge clk) counter <= counter + 1;

in main, i...
also have the same clk.
what i am looking to do is have the output of counter go into the input
of main.

i tried wire, assign and a bunch of other stuff.

this is what i am thinking
1. counter and main are in sink cause they use the same clk.
2. is my counter value lost when i go out of instantiated counter?
3. if need be i can cut/paste my two modules

thanks

 

[Jason Zheng]

pat wrote:

i have 2 modules.
one i call 'main'
one is called 'counter' which is instantiated in main.

main has...
clk input
counter_input
[7:0] output

counter has...
clk input
counter output

(i am using xilinx web pack verilog design (not schematic design)

i instantiate counter in main sending it clk only. inside counter i
have always @(posedge clk) counter <= counter + 1;

in main, i...
also have the same clk.
what i am looking to do is have the output of counter go into the input
of main.

i tried wire, assign and a bunch of other stuff.

this is what i am thinking
1. counter and main are in sink cause they use the same clk.
2. is my counter value lost when i go out of instantiated counter?
3. if need be i can cut/paste my two modules

thanks

Don't make the clk signal an input for main. Instead, make it a regular

wire, and supply it to the output of the clk instance.

e.g.,

module main();
wire clock;
clk clk_(clock);
endmodule //main

module clk(clock);
output clock;
reg clock;

always #(CLK_CYCLE/2) clock = ~clock;

initial clock = 0;
endmodule //clk

 

[Ajeetha Kumari]

Hi,
Try:

module cntr (input clk, output reg [3:0] cnt);

// logic to update cntr - is it all that tough
// BTW - why you don't have a reset??

endmodule

module main (input clk);
wire [3:0] cnt;
cntr u_cntr (.clk(clk), .cnt(cnt) )
endmodule

HTH,
Ajeetha
http://www.noveldv.com

pat <me@here.com> wrote in message news:<pan.2004.09.08.01.18.03.387623@here.com>...

i have 2 modules.
one i call 'main'
one is called 'counter' which is instantiated in main.

main has...
clk input
counter_input
[7:0] output

counter has...
clk input
counter output

(i am using xilinx web pack verilog design (not schematic design)

i instantiate counter in main sending it clk only. inside counter i
have always @(posedge clk) counter <= counter + 1;

in main, i...
also have the same clk.
what i am looking to do is have the output of counter go into the input
of main.

i tried wire, assign and a bunch of other stuff.

this is what i am thinking
1. counter and main are in sink cause they use the same clk.
2. is my counter value lost when i go out of instantiated counter?
3. if need be i can cut/paste my two modules

thanks

 

[Steven Sharp]

pat <me@here.com> wrote in message news:<pan.2004.09.08.01.18.03.387623@here.com>...

i have 2 modules.
one i call 'main'
one is called 'counter' which is instantiated in main.

i instantiate counter in main sending it clk only. inside counter i
have always @(posedge clk) counter <= counter + 1;

in main, i...
also have the same clk.
what i am looking to do is have the output of counter go into the input
of main.

You appear to be confused about how port connections work. If
counter is instantiated inside main, any outputs from counter will
come out of counter through ports of counter. They will go to
whatever you have connected to the instance of counter inside main.
All communication between main and counter will go through the
ports of the counter instance.

The input ports of main are not for connecting to things instantiated
inside main. They are for connecting main to whatever instantiates
main (or the "outside" if main is a top-level module).