2 inverters in series

Hi

Is there some trick that your can do so that when assigning 2 inverter
in series, that they won't get "optimised" away. I don't know why I
need this, but it would be cool to do. Thanks. I know this not really
about verilog, but it would be great if I can do it using verilog
without using schematics.

 

[mike]

Jason Zheng <xin.zheng@jpl.nasa.gov> wrote in message news:<d2rsvr$ndj$1@nntp1.jpl.nasa.gov>...

perltcl@yahoo.com wrote:
Hi

Is there some trick that your can do so that when assigning 2 inverter
in series, that they won't get "optimised" away. I don't know why I
need this, but it would be cool to do. Thanks. I know this not really
about verilog, but it would be great if I can do it using verilog
without using schematics.

For synplify, I think you need to use "syn_keep" directive on the output
net to preserve the seemingly redundant logic. There might be use for
this on some specialty circuits, such as some interfacing logic between
two clock domains. But other than that, I don't know why you would need it.

-jz
regards:

good post

thank you
May goodness be with you all