1653 - At least one timing constraint is impossible to meet

S

spacetimerake

Guest
Hi All,

I am compiling a SOPC project with a user developed IP. When I compilin
the user IP alone, everything is fine, no error reported. However when
compiling the SOPC project (user IP+ microblaze soft core + some xilinx I
cores), I got the following error message:

Pack:1653 - At least one timing constraint is impossible to meet because
component delays alone exceed the constraint......

The log is as follows:

INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place an
Route
timing report.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case |
Best Case | Timing | Timing
| | Slack
Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_SI | SETUP | -0.723ns|
7.781ns| 18| 7173
G_DCM0_CLKFX = PERIOD TIMEGRP "clock_gene | HOLD | 0.188ns|
| 0| 0
rator_0_clock_generator_0_SIG_DCM0_CLKFX" | | |
| |
TS_sys_clk_pin * 2.4 HIGH 50% | | |
| |
----------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_SI | SETUP | 3.303ns|
3.394ns| 0| 0
G_DCM0_CLK0 = PERIOD TIMEGRP "clock_gener | HOLD | -0.456ns|
| 288| 24751
ator_0_clock_generator_0_SIG_DCM0_CLK0" T | | |
| |
S_sys_clk_pin HIGH 50% | | |
| |
----------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_SI | SETUP | -0.404ns|
29.688ns| 4| 1612
G_DCM0_CLKDV = PERIOD TIMEGRP "clock_gene | HOLD | -0.189ns|
| 497| 9610
rator_0_clock_generator_0_SIG_DCM0_CLKDV" | | |
| |
TS_sys_clk_pin / 2 HIGH 50% | | |
| |
----------------------------------------------------------------------------------------------------------
* NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_I | SETUP | 12.323ns|
4.791ns| 0| 0
BUF" PERIOD = 40 ns HIGH 14 ns | HOLD | -0.186ns|
| 48| 5976

...........

However, I did not set any timing constrains in the UCF file. The abov
timing constrains were generate by the system in the system.pcf file.

It seems that the error is caused by a DCM, it looks very strange. If
compile the system without user IP, no error reported. If I compile th
user IP alone, still no error. However, if I compile the whole system
user IP, the error appeared. Can anyone kindly tell me how to solve thi
problem?


Many thanks!

regards

sam




---------------------------------------
Posted through http://www.FPGARelated.com
 
Do you have 2 DCMs in your design? You might have a clock generator in th
processor module and another dcm external to the processor.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Do you have 2 DCMs in your design? You might have a clock generator i
the
processor module and another dcm external to the processor.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
Thanks for the reply.
I did not use any DCM in my design. The clock I used is generated using th
clock generator IP core of xilinx. This IP core can support up to 15 clock
I use its 4th out put . I define the following parameter in the mhs fil
and the code is as follows:

# #######################
PARAMETER C_CLKOUT4_FREQ = 240000000
PARAMETER C_CLKOUT4_PHASE = 0
PARAMETER C_CLKOUT4_GROUP = NONE
PARAMETER C_CLKOUT4_BUF = TRUE
# #########################
PORT CLKOUT4 = clk_240_0000MHz

PORT clk_240MHz = clk_240_0000MHz

I really do not understand why there is no error if I compiling the
separately.





---------------------------------------
Posted through http://www.FPGARelated.com
 
On Sun, 28 Nov 2010 23:17:49 -0600, "spacetimerake"
<spacetimerake@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote:

Do you have 2 DCMs in your design? You might have a clock generator in
the
processor module and another dcm external to the processor.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com


Thanks for the reply.
I did not use any DCM in my design. The clock I used is generated using the
clock generator IP core of xilinx. This IP core can support up to 15 clock.
I use its 4th out put . I define the following parameter in the mhs file
and the code is as follows:

# #######################
PARAMETER C_CLKOUT4_FREQ = 240000000
PARAMETER C_CLKOUT4_PHASE = 0
PARAMETER C_CLKOUT4_GROUP = NONE
PARAMETER C_CLKOUT4_BUF = TRUE
# #########################
PORT CLKOUT4 = clk_240_0000MHz

PORT clk_240MHz = clk_240_0000MHz

I really do not understand why there is no error if I compiling them
separately.
Click to expand...
When you compile your ip block separately do you set a 240 MHz clock
constraint on it? Do you also constrain your input?
What's probably happening is that you have unconstrained input on your
ip block with a long delay and when you make your integrated block
this path shows up. You have to look at the actual path which is
failing. It's probably from a register in the bus (PLB?)
implementation through some combination logic in your block to a
register in your block. Make your peripheral implementation a
registered one ie register the bus data before you use it.
Most importantly make sure that your ip is properly constrained when
you synthesize it by itself.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
 
On Sun, 28 Nov 2010 23:17:49 -0600, "spacetimerake"
spacetimerake@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com> wrote:

Do you have 2 DCMs in your design? You might have a clock generator in
the
processor module and another dcm external to the processor.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com


Thanks for the reply.
I did not use any DCM in my design. The clock I used is generated usin
the
clock generator IP core of xilinx. This IP core can support up to 1
clock.
I use its 4th out put . I define the following parameter in the mhs file
and the code is as follows:

# #######################
PARAMETER C_CLKOUT4_FREQ = 240000000
PARAMETER C_CLKOUT4_PHASE = 0
PARAMETER C_CLKOUT4_GROUP = NONE
PARAMETER C_CLKOUT4_BUF = TRUE
# #########################
PORT CLKOUT4 = clk_240_0000MHz

PORT clk_240MHz = clk_240_0000MHz

I really do not understand why there is no error if I compiling them
separately.

When you compile your ip block separately do you set a 240 MHz clock
constraint on it? Do you also constrain your input?
What's probably happening is that you have unconstrained input on your
ip block with a long delay and when you make your integrated block
this path shows up. You have to look at the actual path which is
failing. It's probably from a register in the bus (PLB?)
implementation through some combination logic in your block to a
register in your block. Make your peripheral implementation a
registered one ie register the bus data before you use it.
Most importantly make sure that your ip is properly constrained when
you synthesize it by itself.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
Click to expand...

Problem solved, thank you so much for the help!!



---------------------------------------
Posted through http://www.FPGARelated.com
 
"spacetimerake" <spacetimerake@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com>
writes:

I did not use any DCM in my design. The clock I used is generated using the
clock generator IP core of xilinx. This IP core can support up to 15 clock.
I use its 4th out put . I define the following parameter in the mhs file
and the code is as follows:
Click to expand...
Just for completeness, that IP core will create as many DCMs as it
needs to create the clock outputs you've asked for.

Cheers
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
 
"spacetimerake" <spacetimerake@n_o_s_p_a_m.n_o_s_p_a_m.hotmail.com
writes:

I did not use any DCM in my design. The clock I used is generated usin
the
clock generator IP core of xilinx. This IP core can support up to 1
clock.
I use its 4th out put . I define the following parameter in the mh
file
and the code is as follows:

Just for completeness, that IP core will create as many DCMs as it
needs to create the clock outputs you've asked for.

Cheers
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
Click to expand...
Thank you so much for the reply. From the log, it seems that the system i
trying to adding a constrain for the DCM0 to generate a 240MHz clock, tha
is what I am using for the user IP. So when I manually add a constrain fo
that clock, the error was solved.

Any way, thank you so much for the help! And thanks for this web site. I
is really a good place to learning!

sam


---------------------------------------
Posted through http://www.FPGARelated.com
 
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