10BASE-T Clock Recovery PLL

[Andrew Holme]

Just for fun, I'm trying to design a PLL for 10Mbps 10BASE-T Ethernet
clock recovery.

The VXCO is Kvco = 133 Hz/volt = 838 radians/volt-second. The digital
phase detctor has a charge pump output with Kpd = 0.7 mA/radian. The
comparison frequency is 10 MHz.

The 10BASE-T frame has a 64 bit preamble which allows the receiver
time to synchronise. The loop needs to lock in 6.4 micro-seconds
demanding a wide bandwidth. My question is: how wide? 40 KHz?? The
first quadrant of a 40 KHz sine wave is 6.25 micro-seconds.

I'm doing Bode plots for various loop filters using C++. I don't have
any fancy simulation software. Maybe it's time to get some??

Worryingly, my design seems to be calling for impractical component
values. For example, a loop filter consisting of (22pF || 180k) in
series with 470pF has a -3dB point of only around 27 KHz.

Is it ever going to work?

On the plus side, the lock doesn't need to be perfect after 6.4
micro-seconds - just good enough to recover data. Lock can only
improve during the data bits. I don't care about phase noise.

I wonder if I need DC steering to keep the control voltage mid-rail in
the absense of data pulses? Without it, the phase detector will push
the VCO down to Fmin between packets.

Andrew.

 

[Terry Given]

"Andrew Holme" <ajholme@hotmail.com> wrote in message
news:966757eb.0405030249.328e92fc@posting.google.com...

Just for fun, I'm trying to design a PLL for 10Mbps 10BASE-T Ethernet
clock recovery.

The VXCO is Kvco = 133 Hz/volt = 838 radians/volt-second. The digital
phase detctor has a charge pump output with Kpd = 0.7 mA/radian. The
comparison frequency is 10 MHz.

The 10BASE-T frame has a 64 bit preamble which allows the receiver
time to synchronise. The loop needs to lock in 6.4 micro-seconds
demanding a wide bandwidth. My question is: how wide? 40 KHz?? The
first quadrant of a 40 KHz sine wave is 6.25 micro-seconds.

I'm doing Bode plots for various loop filters using C++. I don't have
any fancy simulation software. Maybe it's time to get some??

google "scilab" - its a freeware maths program, a bit like matlab. very
powerful, not IMO too buggy

Worryingly, my design seems to be calling for impractical component
values. For example, a loop filter consisting of (22pF || 180k) in
series with 470pF has a -3dB point of only around 27 KHz.

Is it ever going to work?

On the plus side, the lock doesn't need to be perfect after 6.4
micro-seconds - just good enough to recover data. Lock can only
improve during the data bits. I don't care about phase noise.

I wonder if I need DC steering to keep the control voltage mid-rail in
the absense of data pulses? Without it, the phase detector will push
the VCO down to Fmin between packets.

Andrew.

 

[Allan Herriman]

On 3 May 2004 03:49:15 -0700, ajholme@hotmail.com (Andrew Holme)
wrote:

Just for fun, I'm trying to design a PLL for 10Mbps 10BASE-T Ethernet
clock recovery.

You have an interesting idea of fun. It should be a good learning
experience for you.


You should consider that no practical 10BASE-T clock recovery circuit
(that I am aware of) uses a VCXO.

As you have found, the low Kvco makes it difficult to lock during the
preamble.

A VCXO has a modulation bandwidth of (usually) no more than a few tens
of kHz. This is equivalent to an extra pole in the transfer
characteristic, and makes it difficult to design a stable loop with a
closed loop bandwidth of more than a few kHz.

Is it ever going to work?

Possibly, if you change to a VCO (e.g. an RC or LC osc), with much
higher Kvco.

On the plus side, the lock doesn't need to be perfect after 6.4
micro-seconds - just good enough to recover data. Lock can only
improve during the data bits. I don't care about phase noise.

Consider following the VCO with a phase rotator, which would allow you
to jump to the correct phase instantly during the preamble without
having to adjust the VCO.
The phase rotator could be as simple as using a higher frequency VCO
and following it with (say) a divide by 4 counter with quadrature
outputs and a mux. The mux may need to be glitchless - this sort of
thing is easier to achieve on an ASIC than by using discrete parts.

Some clock recovery circuits use a fixed frequency reference and use a
phase rotator to shift the frequency (by continuously rotating the
phase).

I wonder if I need DC steering to keep the control voltage mid-rail in
the absense of data pulses? Without it, the phase detector will push
the VCO down to Fmin between packets.

You could switch the PLL reference to a local 10MHz fixed XTAL osc in
the absence of input pulses. This will keep the PLL centred, and
reduce aquisition time. This probably isn't a problem when using a
VCXO, but would definitely be required if using an RC VCO.


Yet another way to tackle the problem is to use a much higher
frequency fixed clock and design a DPLL inside an FPGA.

Or you could just buy a PHY chip

Regards,
Allan.

 

[Jim Thompson]

On Tue, 04 May 2004 13:06:14 +1000, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

On 3 May 2004 03:49:15 -0700, ajholme@hotmail.com (Andrew Holme)
wrote:

Just for fun, I'm trying to design a PLL for 10Mbps 10BASE-T Ethernet
clock recovery.

You have an interesting idea of fun. It should be a good learning
experience for you.


You should consider that no practical 10BASE-T clock recovery circuit
(that I am aware of) uses a VCXO.

As you have found, the low Kvco makes it difficult to lock during the
preamble.

A VCXO has a modulation bandwidth of (usually) no more than a few tens
of kHz. This is equivalent to an extra pole in the transfer
characteristic, and makes it difficult to design a stable loop with a
closed loop bandwidth of more than a few kHz.

Is it ever going to work?

Possibly, if you change to a VCO (e.g. an RC or LC osc), with much
higher Kvco.

On the plus side, the lock doesn't need to be perfect after 6.4
micro-seconds - just good enough to recover data. Lock can only
improve during the data bits. I don't care about phase noise.

Consider following the VCO with a phase rotator, which would allow you
to jump to the correct phase instantly during the preamble without
having to adjust the VCO.
The phase rotator could be as simple as using a higher frequency VCO
and following it with (say) a divide by 4 counter with quadrature
outputs and a mux. The mux may need to be glitchless - this sort of
thing is easier to achieve on an ASIC than by using discrete parts.

Some clock recovery circuits use a fixed frequency reference and use a
phase rotator to shift the frequency (by continuously rotating the
phase).

I wonder if I need DC steering to keep the control voltage mid-rail in
the absense of data pulses? Without it, the phase detector will push
the VCO down to Fmin between packets.

You could switch the PLL reference to a local 10MHz fixed XTAL osc in
the absence of input pulses. This will keep the PLL centred, and
reduce aquisition time. This probably isn't a problem when using a
VCXO, but would definitely be required if using an RC VCO.


Yet another way to tackle the problem is to use a much higher
frequency fixed clock and design a DPLL inside an FPGA.

Or you could just buy a PHY chip

Regards,
Allan.

See "ShiftRegisterPLL.pdf" and "SyncRingOsc.pdf" on the
S.E.D/Schematics Page of my website.

I've done a number of these "jerk-able phase" systems. I like them
because they can handle missing transitions without going off into
la-la land.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice480)460-2350 | |
| E-mail Address at Website Fax480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

 

[Andrew Holme]

Thank you, Allan and Terry.

Setting Kvco much higher, I can now get wide bandwidth with sensible
component values. I think I'll use an LC oscillator.

To my bode plot tabulator, I've added a GUI with scroll bars to set
component values but I really want to plot gain/phase graphically.
That would give me a more intuitive feel for how the values interact.
It's hard to take in columns of figures! I'll try scilab.

I know how to evaluate stability / phase margin using bode plots, but
I notice that some people design phase locked loops using natural
frequency and damping factor. I have a few worked examples of this
method in (Plessey) data books but no reference material on it. Can
anyone recommend any good bed time reading - preferably, covering both
2nd and 3rd order loops?

I'm also looking for ways to estimate settling time.

Thanks,
Andrew.


Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<du0e90pjq4c7es0aiqruvjkjhdsqj9d2st@4ax.com>...

On 3 May 2004 03:49:15 -0700, ajholme@hotmail.com (Andrew Holme)
wrote:

Just for fun, I'm trying to design a PLL for 10Mbps 10BASE-T Ethernet
clock recovery.

You have an interesting idea of fun. It should be a good learning
experience for you.


You should consider that no practical 10BASE-T clock recovery circuit
(that I am aware of) uses a VCXO.

As you have found, the low Kvco makes it difficult to lock during the
preamble.

A VCXO has a modulation bandwidth of (usually) no more than a few tens
of kHz. This is equivalent to an extra pole in the transfer
characteristic, and makes it difficult to design a stable loop with a
closed loop bandwidth of more than a few kHz.

Is it ever going to work?

Possibly, if you change to a VCO (e.g. an RC or LC osc), with much
higher Kvco.

On the plus side, the lock doesn't need to be perfect after 6.4
micro-seconds - just good enough to recover data. Lock can only
improve during the data bits. I don't care about phase noise.

Consider following the VCO with a phase rotator, which would allow you
to jump to the correct phase instantly during the preamble without
having to adjust the VCO.
The phase rotator could be as simple as using a higher frequency VCO
and following it with (say) a divide by 4 counter with quadrature
outputs and a mux. The mux may need to be glitchless - this sort of
thing is easier to achieve on an ASIC than by using discrete parts.

Some clock recovery circuits use a fixed frequency reference and use a
phase rotator to shift the frequency (by continuously rotating the
phase).

I wonder if I need DC steering to keep the control voltage mid-rail in
the absense of data pulses? Without it, the phase detector will push
the VCO down to Fmin between packets.

You could switch the PLL reference to a local 10MHz fixed XTAL osc in
the absence of input pulses. This will keep the PLL centred, and
reduce aquisition time. This probably isn't a problem when using a
VCXO, but would definitely be required if using an RC VCO.


Yet another way to tackle the problem is to use a much higher
frequency fixed clock and design a DPLL inside an FPGA.

Or you could just buy a PHY chip

Regards,
Allan.