0-padding in verilog 2001

[Jason Zheng]

wire x[127:0] = y[68:0];

In verilog 2001, would the upper bits of x be padded with zero's or x's?

 

[Pooja Maheshwari]

Jason Zheng wrote:

;

In verilog 2001, would the upper bits of x be padded with zero's or x's?

If the MSB of y i.e. y[68] is 'X', it will be padded with x's.
If the MSB of y is 'Z', it will be padded with z's.
In all other cases (0/1), it will be padded with 0's.

- Pooja

 

[Neo]

Jason Zheng <jzheng@jpl.nasa.gov> wrote in message news:<co3bq5$8er$1@nntp1.jpl.nasa.gov>...

;

In verilog 2001, would the upper bits of x be padded with zero's or x's?

They are stuffed with zeros.

 

[Steven Sharp]

Jason Zheng <jzheng@jpl.nasa.gov> wrote in message news:<co3bq5$8er$1@nntp1.jpl.nasa.gov>...

;

In verilog 2001, would the upper bits of x be padded with zero's or x's?

They will be padded with zeroes. The width of the right-hand-side
expression is the maximum of its own width and the width of the left-
hand-side, or 128. The RHS expression is also unsigned (even if y is
declared signed, a part-select is always unsigned). So when the operand
y[68:0] is extended to the width of the expression, it is extended as
an unsigned value, which means zero-extension.

If you used "x = y;" and y were signed, then the value of y would be
sign-extended instead of zero-extended.

 

[Steven Sharp]

Pooja Maheshwari <mpooja@agere.com> wrote in message news:<41A59ECA.FBCBA51E@agere.com>...

If the MSB of y i.e. y[68] is 'X', it will be padded with x's.
If the MSB of y is 'Z', it will be padded with z's.
In all other cases (0/1), it will be padded with 0's.

There are special rules similar to this for constant literals, to
make it easier to specify constants without having to specify a lot
of upper bits. However, these are not the general rules applied in
extending operands in expressions.