0.13u device with 5V I/O

[Jim Granville]

News info below.
Automotive customers tend to be tough on reliability, and on
standard supply voltages.

Of interest in this release are

+ 0.13u/150MHz core, but they manage to deliver 5V I/O, ADCs etc
[ FPGA vendors could learn from this ]

+ Comment on error correcting FLASH

Not mentioned here, but also noted, is the trend to require
a Vpp or PGM enable pin, on Automotive FLASH parts.
Seems to be a concern about shipping a part that MIGHT be able to
re-program its own flash ?

- jg

Motorola news item :
"Based on 0.13-micron design rules, the MPC5554 chip operates at speeds
of 50 to 150MHz. Though the design rules are advanced, Motorola made the
part so that its I/O and ADC will run at 5V, which automakers often
prefer.

The company also said it designed the flash memory to be more reliable
by adding error correcting code. The flash is built to retain data for
20 years and withstand 100,000 read/erase cycles. The first MPC5554 will
include 2 Mbytes of flash, and the company is planning to come out with
a 4Mbyte version next year, Cornyn said. "

 

[Eric Crabill]

Hi,

+ 0.13u/150MHz core, but they manage to deliver 5V I/O,
ADCs etc [ FPGA vendors could learn from this ]

I think your last comment is unfair. I'm sure their 5V I/O
doesn't even begin to approach the performance levels that
you can obtain from the programmable I/O in recent FPGAs.

There's nothing impossible about 5V I/O using .13u (or 90 nm).
It just takes more processing steps, which means more $$$ to
build the chip. On top of that, the structures that would
result may be good for 5V I/O, but not for 840 Mbps LVDS...

I believe the "features" available in recent FPGAs is the
result of market forces at work.

Eric

 

[Jim Granville]

Eric Crabill wrote:

Hi,

+ 0.13u/150MHz core, but they manage to deliver 5V I/O,
ADCs etc [ FPGA vendors could learn from this ]

I think your last comment is unfair. I'm sure their 5V I/O
doesn't even begin to approach the performance levels that
you can obtain from the programmable I/O in recent FPGAs.

There are many different units to measure 'performance levels',
- if you choose VOLTS, then they actually exceed recent FPGA.
- if you choose MHz of LVDS IO, then clearly FPGA exceeds
the uC, as the uC does not even offer LVDS....

There's nothing impossible about 5V I/O using .13u (or 90 nm).
It just takes more processing steps, which means more $$$ to
build the chip. On top of that, the structures that would
result may be good for 5V I/O, but not for 840 Mbps LVDS...

Can you think of an instance where a customer would need
both at once, on the same pin ?

I believe the "features" available in recent FPGAs is the
result of market forces at work.

That's one spin on it. A more realistic pathway may be
(significant) process improvements, and market guesses

The point is, if FPGA wish to broaden their market with
processor cores, and so play in the larger controller sandpit,
they are going to have to address issues that normally
go into the 'too hard / not enough market' reflex-box.

Over the recent few years 5V IO has been added-back to a number
of uC devices, where 'process rush' meant it was 'improved out'.
They found out the hard way, that lack of 5V IO => fewer design wins.

Error correcting Code storage (2MB Flash) was interesting to see,
in the Motorola uC, as I am sure that was not a zero cost item,
but the result of 'market forces' == customer demand for reliability.

-jg

 

[Garden Gnome]

Five volts would have been nice for some incremental respins of older
products. Instead I had to level translate (using an IDT device) which was
$$$, real estate etc. I definitely would have liked it to be supported in
the FPGA.


"Eric Crabill" <eric.crabill@xilinx.com> wrote in message
news:3FAD83C7.8C6E6C71@xilinx.com...

Hi,

+ 0.13u/150MHz core, but they manage to deliver 5V I/O,
ADCs etc [ FPGA vendors could learn from this ]

I think your last comment is unfair. I'm sure their 5V I/O
doesn't even begin to approach the performance levels that
you can obtain from the programmable I/O in recent FPGAs.

There's nothing impossible about 5V I/O using .13u (or 90 nm).
It just takes more processing steps, which means more $$$ to
build the chip. On top of that, the structures that would
result may be good for 5V I/O, but not for 840 Mbps LVDS...

I believe the "features" available in recent FPGAs is the
result of market forces at work.

Eric

 

[Eric Crabill]

Hi,

Five volts would have been nice for some incremental respins
of older products. Instead I had to level translate (using an
IDT device) which was $$$, real estate etc. I definitely would
have liked it to be supported in the FPGA.

Don't get me wrong. As a standard bus interface IP developer
(PCI, PCI-X, and now PCI Express...) I like 5V I/O even more
than the next guy. I'd love to be able to directly support
5V PCI on newer Xilinx parts without external components.

What I was trying to point out is that the economic/market
reality of 5V support on newer FPGA devices has resulted in
a tradeoff: faster, low voltage I/O and less costly devices
at the expense of 5V I/O support.

I believe every major programmable logic manufacturer has
made this tradeoff. It isn't Xilinx trying to alienate
users of 5V logic. If someone can show me a commercial
FPGA at .15u or below that has real 5V I/O support, I'll
eat humble pie.

Like you pointed out, those who need a lot of 5V I/O end up
paying for it, either by using older parts (more $/logic)
or external (more $) components such as level translators.
It is the unfortunate cost of designing with I/O signaling
levels that are no longer mainstream.

Speaking entirely for myself,
Eric

 

[Eric Crabill]

Hi,

There are many different units to measure 'performance levels',
- if you choose VOLTS, then they actually exceed recent FPGA.
- if you choose MHz of LVDS IO, then clearly FPGA exceeds
the uC, as the uC does not even offer LVDS....

I'd agree with that, if you are looking at a 5V application
then high speed LVDS I/O probably doesn't get you very far...

Can you think of an instance where a customer would need
both at once, on the same pin ?

For a general purpose FPGA, with general purpose programmable
I/O, you need this on every pin... While the end user makes
a selection via the bitstream, the actual hardware has to be
capable of handling all possible configurations.

On recent devices, 5V I/O is gone... I would not be surprised
if it's the same issue all over again with 3.3V in a few years.

As I had mentioned, it is possible to build a device to support
5V I/O. That device will cost more for everyone, even if they
are not using 5V I/O. Those I/O will also be slower. I believe
few people would buy these parts, due to the higher cost and
lower performance.

There are other approaches -- things like dedicated banks of I/O
just for a specific purpose. Xilinx uses this for the gigabit
serial transceivers in V2pro. One could do something similar
but for a bank of 5V I/O. For 5V I/O, it would still make the
devices more expensive.

I do not believe making general purpose devices more expensive
to cater to a declining market is a good business decision. I
think, for better or worse, we're all being swept along by the
tide of economics.

The point is, if FPGA wish to broaden their market with
processor cores, and so play in the larger controller
sandpit, they are going to have to address issues that
normally go into the 'too hard / not enough market'
reflex-box.

If there's "not enough market" I doubt anyone trying to make
money is going to address it. If there were a significant
market, but there were technical hurdles, I am sure people
here, and at other FPGA vendors, would be researching a way
to cash in on it.

In the near future, I don't think the FPGA will be a direct
drop in replacement for a controller with tons of 5V I/O.

The vision of a programmable system is that the entire system
goes into the FPGA. What might have been 5V signals between
all the modules are now low voltage signals running over the
internal FPGA routing, because almost everything is iniside
the FPGA. There will still be things outside. But most of
those that use a large number of I/O (large memories, etc...)
are no longer designed with 5V I/0. A quick survey of Micron,
Cypress, and IDT websites will confirm this.

For smaller RAMs (things like a 6116, etc...) those can be
implemented in the FPGA block memory. So the need for these
things with high pincount 5V I/O goes away...

I'm not denying that you will need 5V I/O. Just that you
probably don't need much, unless you're doing a legacy
design, and in that case you might anticipate having to
pay for a feature that is not in "mainstream" use anymore.
That's how it appears to me, at least in the FPGA market...

These are entirely my opinions,
Eric

 

[Garden Gnome]

What I was trying to point out is that the economic/market
reality of 5V support on newer FPGA devices has resulted in
a tradeoff: faster, low voltage I/O and less costly devices
at the expense of 5V I/O support.

You do get the speed for these new I/O voltages - for new designs this is
great. I was wondering if Xilinx et al considers respins a design win as
well? I've been presented with the situation that if we can upgrade
performance/function on an existing 5V design the benifits are faster
market and lower test risk. I believe the major concern for a 5V I/O
sink/source pin is capacitance regardless of the speed it's used at. I'd
like to see 5V I/O, or an acceptable work-around while still meeting the
requirements of the other speeds.

 

[Hal Murray]

Don't get me wrong. As a standard bus interface IP developer
(PCI, PCI-X, and now PCI Express...) I like 5V I/O even more
than the next guy. I'd love to be able to directly support
5V PCI on newer Xilinx parts without external components.

What's the newest/best/cheapest part that's reasonable to
connect to old 5V PCI?

Is there a legal recipe using external parts? I'd expect
that approach would have troubles meeting the loading rules.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Jim Granville]

Eric Crabill wrote:

Hi,

snip
Can you think of an instance where a customer would need
both at once, on the same pin ?

For a general purpose FPGA, with general purpose programmable
I/O, you need this on every pin... While the end user makes
a selection via the bitstream, the actual hardware has to be
capable of handling all possible configurations.

Not true. Some of the more esoteric IOs are already 'blocked'
Users could live with not having 5V IO on every single IO,
jus like they live with not having 840MHz SerDes on every IO.

On recent devices, 5V I/O is gone... I would not be surprised
if it's the same issue all over again with 3.3V in a few years.

Depends on where you look, and why.
On embedded controllers, 5V is actually making a comeback.
Lattices' very newest CPLDs, added 5V tolerant IOs.

On chip regulators are also appearing, as other vendors look
at ways to expand the use-ability of the shrink silicon.

As I had mentioned, it is possible to build a device to support
5V I/O. That device will cost more for everyone, even if they
are not using 5V I/O. Those I/O will also be slower. I believe
few people would buy these parts, due to the higher cost and
lower performance.

Give the customers some hard numbers, and let them decide for
themselves

I see Hynix have just released a high voltage 0.18u process,
that targets LCD display drivers (so high voltage here means
40-50V region )

There are other approaches -- things like dedicated banks of I/O
just for a specific purpose. Xilinx uses this for the gigabit
serial transceivers in V2pro. One could do something similar
but for a bank of 5V I/O. For 5V I/O, it would still make the
devices more expensive.

Some numbers ? XX cents per pin ?

The point is, if FPGA wish to broaden their market with
processor cores, and so play in the larger controller
sandpit, they are going to have to address issues that
normally go into the 'too hard / not enough market'
reflex-box.

If there's "not enough market" I doubt anyone trying to make
money is going to address it. If there were a significant
market, but there were technical hurdles, I am sure people
here, and at other FPGA vendors, would be researching a way
to cash in on it.

They are already.
Wider Vcc range devices are appearing, you just have to look
for them (they are not appearing in FPGA markets first).
Narrow/lowered/restricted Vcc devices have been replaced
by better engineered, wider Vcc ones.

There was an interesting earlier thread that touched on leakage
failure modes in higher IO on the finest processes.

-jg

 

[rickman]

Hal Murray wrote:

Don't get me wrong. As a standard bus interface IP developer
(PCI, PCI-X, and now PCI Express...) I like 5V I/O even more
than the next guy. I'd love to be able to directly support
5V PCI on newer Xilinx parts without external components.

What's the newest/best/cheapest part that's reasonable to
connect to old 5V PCI?

Is there a legal recipe using external parts? I'd expect
that approach would have troubles meeting the loading rules.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

The newest 5 volt tolerant parts that Xilinx has are the Virtex /
Spartan II lines. But they both have high startup current
requirements. They have recently refined these requirements, but they
are still very high relative to the normal currents and require special
attention to power supply design, especially if you are using industrial
temp parts.

On the 5 volt IO parts without the high startup current requirement,
Xilinx has no parts that are fully supported with current software.
They still recommend the old Spartan XL parts for new designs, but they
are only supported with old software which is poorly supported by the
hotline. Because of that and the poor price/function ratio, we chose a
different vendor.

Altera has the ACEX line of parts which are still fully supported by the
current software. They are also newer parts (~2 years old) which should
be available for a long time to come.

BTW, on the price issue, I have found that both vendors will
substantially cut their prices to get a design win. If you talk
directly to the FPGA vendor's rep you can get 50% or larger reduction in
price for moderate volumes.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Eric Crabill]

Hi,

You can use Virtex or Spartan-II to interface with 5V PCI bus
and retain full compliance per the specification. You can use
any of our devices, even Spartan3 and Virtex2Pro, with the 5V
PCI bus, but you need some level translators. This is certainly
a functional solution (I've tested it personally) but it is not
compliant with the letter of the specifications.

The specifications are pretty clear that you are allowed only
one component, and that is your "PCI component" and all bus
signals must attach directly to that one component.

Eric

Hal Murray wrote:

Don't get me wrong. As a standard bus interface IP developer
(PCI, PCI-X, and now PCI Express...) I like 5V I/O even more
than the next guy. I'd love to be able to directly support
5V PCI on newer Xilinx parts without external components.

What's the newest/best/cheapest part that's reasonable to
connect to old 5V PCI?

Is there a legal recipe using external parts? I'd expect
that approach would have troubles meeting the loading rules.

 

[Eric Crabill]

Hi Jim,

I see we have a difference of opinion. I'm not going to try to
change your mind, only answer the additional questions you posed:

For a general purpose FPGA, with general purpose programmable
I/O, you need this on every pin... While the end user makes
a selection via the bitstream, the actual hardware has to be
capable of handling all possible configurations.

Not true. Some of the more esoteric IOs are already 'blocked'
Users could live with not having 5V IO on every single IO,
jus like they live with not having 840MHz SerDes on every IO.

There are no Xilinx devices like this. With the exception of
the gigabit serial I/O, all I/O pins are the same.

There are some vendors that have banking rules like you have
described, but even so, those banks don't support 5V I/O.

Depends on where you look, and why.
On embedded controllers, 5V is actually making a comeback.
Lattices' very newest CPLDs, added 5V tolerant IOs.

I am looking specifically at the FPGA market.

Give the customers some hard numbers, and let them decide for
themselves

Most vendors have limited resources, and so make intelligent
guesses about price/feature tradeoffs. The market is wide open
for someone do exactly what you suggest.

Some numbers ? XX cents per pin ?

I don't have this information. If I did, I'm sure my employer
would not be pleased if I were to share it. However, I do know
that the expense is considerable:

1. Additional mask sets.
2. Additional processing steps.
3. Cost of lost general purpose I/O.
4. Cost of a low volume, "novelty" product,
including software, support, and documentation.

It would be more expensive. I don't know how much. Time will
tell if FPGA vendors think this is a good return on investment.

Eric

 

[Jim Granville]

Eric Crabill wrote:

snip
Depends on where you look, and why.
On embedded controllers, 5V is actually making a comeback.
Lattices' very newest CPLDs, added 5V tolerant IOs.

I am looking specifically at the FPGA market.

Quite understood.
I am looking from a designers viewpoint, across many markets,
and asking 'why' wrt a specific feature.

Give the customers some hard numbers, and let them decide for
themselves

Most vendors have limited resources, and so make intelligent
guesses about price/feature tradeoffs. The market is wide open
for someone do exactly what you suggest.

Some numbers ? XX cents per pin ?

I don't have this information. If I did, I'm sure my employer
would not be pleased if I were to share it. However, I do know
that the expense is considerable:

1. Additional mask sets.

Accepted - perhaps one more, maybe none with the right cleverness.
Note this mask would not be 0.13u, nor full die area.

2. Additional processing steps.

Yes, and it also requires that the foundry qualify the process,
which requires their customers indicate they need it.

This may come sooner than you think.
I see foundries are now offering 110nm process as a 'back fill'
between the 130nm and 90nm processes.
Seems the customers are not rushing to 90nm quite as
fast as they hoped - so a significant mindset change is occuring
where smallest/fastest is no longer the sole target on the radar.

3. Cost of lost general purpose I/O.

Not sure they are mutually exclusive.
An IC designer could exclude it on some specialist high speed IO.

4. Cost of a low volume, "novelty" product,
including software, support, and documentation.

The other markets releasing 'wide supply' ICs do not think they
are "novelty" products - quite the reverse. Their intention
is to have one die cover as many customers as practical, and
reduce the part number proliferation, as well as extend the
'design life' of a given die.

There are LOTS of benefits along the whole supply chain.

LOGIC has now moved to 1.65-5.5V Vcc specs after some
market failures with lower/narrower offerings.
uC are following, with the better ones now doing 1.8-5.5V,
or 2.0-5.5V - some uC and CPLD have on-die regulators.
When you see the curves, you can appreciate the 1.8-5.5V
was not easy, and not without effort or some silicon cost.

Besides Wide Vcc, commercial temp spec releases are
being dropped in favour of industrial (or wider) 'as standard'.

It would be more expensive. I don't know how much. Time will
tell if FPGA vendors think this is a good return on investment.

See rickmans post, covers the trade-offs designers face and the
reasons for device selection, nicely.

-jg

 

[Larry Doolittle]

In article <3FAFDFB9.63CF0853@xilinx.com>, Eric Crabill wrote:
(posting from a Xilinx e-mail address)

On embedded controllers, 5V is actually making a comeback.
Lattices' very newest CPLDs, added 5V tolerant IOs.

I am looking specifically at the FPGA market.

Give the customers some hard numbers, and let them decide for
themselves

Most vendors have limited resources, and so make intelligent
guesses about price/feature tradeoffs. The market is wide open
for someone do exactly what you suggest.

Ahem. I think your company's lawyers would have something
to say if anyone but you, and maybe Altera, tried anything
of the sort.

- Larry

 

[Eric Crabill]

Hi,

Ahem. I think your company's lawyers would have something
to say if anyone but you, and maybe Altera, tried anything
of the sort.

What about Lattice, Actel, Atmel, and Quicklogic? If I missed
anyone, my apologies in advance...

Also keep in mind that patents expire, and clever people find
other ways to build things that don't infringe. Take a look:

http://eet.com/special/special_issues/1998/timespeople98/sasaki.html

"Basically, the board only said three things," Sasaki remembered.
"Go faster than Xilinx. Don't touch any of their patents..."

Page 15 of http://www.walcek.com/dyna/DY6000.pdf is evidence of
how serious they were about following the board's directives.
Yes, it is programmable logic, but there's no LUT to be found!

Eric

 

[Hal Murray]

You can use Virtex or Spartan-II to interface with 5V PCI bus
and retain full compliance per the specification. You can use
any of our devices, even Spartan3 and Virtex2Pro, with the 5V
PCI bus, but you need some level translators. This is certainly
a functional solution (I've tested it personally) but it is not
compliant with the letter of the specifications.

Do you have any suggested parts for the level translators? I know
about the IDT QuickSwitchs.

The specifications are pretty clear that you are allowed only
one component, and that is your "PCI component" and all bus
signals must attach directly to that one component.

I don't really care about the rules just to check off the
boxes. I'm willing to cheat if I can convince myself (and
some friends?) that the total system will work solidly.

There are two parts to that. One is in limited cases, say one
fewer card on the bus. The other is in any configuration legal
under the specs.

How far did you bend the rules? How much testing/Spicing did
you do?

Do modern FPGAs have a low enough pin capacitance so that the
added capacitance of something like a QuickSwitch fits the old
rules? Or are they fast enough to go through an honest repeater
type chip so there is only one bus load?

Mostly, I'm just curious. If/when I get enough time, I'd like
to build a hobby priced board that I can plug into something like
PCI. For now, that's old 33 MHz 5V PCI. Spartan-II seems like
the best bet. But the clocking in newer chips is attractive.
If there is a solid way to connect them to old PCI, I'd add that
to my list of chips to consider.

Maybe if I wait a bit longer low cost systems will be readily
available that have real 3V PCI slots.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[rickman]

Hal Murray wrote:

You can use Virtex or Spartan-II to interface with 5V PCI bus
and retain full compliance per the specification. You can use
any of our devices, even Spartan3 and Virtex2Pro, with the 5V
PCI bus, but you need some level translators. This is certainly
a functional solution (I've tested it personally) but it is not
compliant with the letter of the specifications.

Do you have any suggested parts for the level translators? I know
about the IDT QuickSwitchs.

TI and other logic makers offer similar products.

The specifications are pretty clear that you are allowed only
one component, and that is your "PCI component" and all bus
signals must attach directly to that one component.

I don't really care about the rules just to check off the
boxes. I'm willing to cheat if I can convince myself (and
some friends?) that the total system will work solidly.

There are two parts to that. One is in limited cases, say one
fewer card on the bus. The other is in any configuration legal
under the specs.

As you must realize, the issue of how you connect to the PCI bus is one
of signal integrity. To use a switch device to limit the voltages to
the FPGA would make significant differences in the signals on the bus.
I expect the routing lengths would be violated even if you could work
around the rest. There are reasons for the specs and violating them
will produce a design that may work in some, but not work with all
systems.

How far did you bend the rules? How much testing/Spicing did
you do?

Do modern FPGAs have a low enough pin capacitance so that the
added capacitance of something like a QuickSwitch fits the old
rules? Or are they fast enough to go through an honest repeater
type chip so there is only one bus load?

I seem to recall that there is one signal pathway that has very little
slack time and even without buffers FPGAs (perhaps ones of a couple
years ago) have a hard time meeting the timing. Add a buffer in one
direction or perhaps both and I expect all your slack is gone and then
some.

The added capacitance of a switch part will be *two* extra pins since
the entire path through the switch to the FPGA will be the true path
(unlike the case with a buffer). I expect this will also be a real
problem in getting close to meeting the specs.

Mostly, I'm just curious. If/when I get enough time, I'd like
to build a hobby priced board that I can plug into something like
PCI. For now, that's old 33 MHz 5V PCI. Spartan-II seems like
the best bet. But the clocking in newer chips is attractive.
If there is a solid way to connect them to old PCI, I'd add that
to my list of chips to consider.

Have you considered the Altera ACEX parts? They are fully 5 volt
tolerant and claim to be PCI compliant, IIRC.

Maybe if I wait a bit longer low cost systems will be readily
available that have real 3V PCI slots.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Nial Stewart]

How far did you bend the rules? How much testing/Spicing did
you do?

Do modern FPGAs have a low enough pin capacitance so that the
added capacitance of something like a QuickSwitch fits the old
rules?

With an Altera Cyclone part the pin capacitance plus that added
by a quickswitch is just within the PCI 10pF/pin spec (Rev2.3)
as long as you keep away from the Vref/IO pins.



Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

 

[Eric Crabill]

Hi,

Do you have any suggested parts for the level translators?

Unfortunately, I do not. I've been dealing with bus switches
because they are bidirectional, which is important for the
application I'm dealing with. There are a number of vendors.

I don't really care about the rules just to check off the
boxes. I'm willing to cheat if I can convince myself (and
some friends?) that the total system will work solidly.

There are many people in this same situation!

There are two parts to that. One is in limited cases, say
one fewer card on the bus. The other is in any configuration
legal under the specs.

We've been looking at the general case, because it is hard
for us to control an end user's bus...

How far did you bend the rules? How much testing/Spicing did
you do?

The Xilinx XAPP646, XAPP653, and XAPP659 application notes are
a good overview of a solutions Xilinx is recommending. These
were developed by the Xilinx applications team. I have not done
any spice simulations, but I have tested these suggestions in
hardware at the PCI Compliance Workshops and have not had any
issues.

If you are using these bus switches for 5V PCI, the only 5V PCI
bus is a 33 MHz, 5V bus. Everything else is 3.3V. In a 33 MHz,
5V bus, our I/O timing has so much slack that the impact of these
switches is next to nothing. It is, however NON-COMPLIANT.

A possible area of concern is in cases where you are also
trying to support other modes, like a Universal 133 MHz PCI-X
card. When such a card is in a 33 MHz, 5V slot, the impact
is again next to nothing...

However, when you put such a design in a 133 MHz PCI-X slot,
you don't have as much slack... I have heard a number of
people comment on this at the PCI Compliance workshops when
they saw what I was testing. I've tested several PCI-X 133
MHz designs using bus switches and have not had any failures.

I have also seen (but not personally tested) customers doing
5V designs using bus switches with VirtexE and Spartan-IIE.

Do modern FPGAs have a low enough pin capacitance so that the
added capacitance of something like a QuickSwitch fits the old
rules? Or are they fast enough to go through an honest repeater
type chip so there is only one bus load?

They are fairly low delay.

Mostly, I'm just curious. If/when I get enough time, I'd like
to build a hobby priced board that I can plug into something like
PCI. For now, that's old 33 MHz 5V PCI. Spartan-II seems like
the best bet. But the clocking in newer chips is attractive.
If there is a solid way to connect them to old PCI, I'd add that
to my list of chips to consider.

I have photoplots for a board that uses the original Virtex at
http://www.engr.sjsu.edu/crabill/projects but if you are looking
at 33 MHz, 5V as your primary mode of operation, I would think
using something newer with bus switches might be more attractive.

Eric